ADV7175 datasheet(17/36 Pages) AD

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ADV7175/ADV7176

REV. A

–17–

SR4

SR3

SR2

SR1

SR0

SR7

SR6

SR5

SR4

SR3 SR2 SR1 SR0

ZERO SHOULD

BE WRITTEN TO

THESE BITS

SR7–SR5

(000)

SUBADDRESS REGISTER

MODE REGISTER 0

MODE REGISTER 1

SUB CARRIER FREQ REGISTER 0

SUB CARRIER FREQ REGISTER 1

SUB CARRIER FREQ REGISTER 2

SUB CARRIER FREQ REGISTER 3

SUB CARRIER PHASE REGISTER

TIMING MODE REGISTER 0

CLOSED CAPTIONING EXTENDED DATA – BYTE 0

CLOSED CAPTIONING EXTENDED DATA – BYTE 1

CLOSED CAPTIONING DATA – BYTE 0

CLOSED CAPTIONING DATA – BYTE 1

TIMING MODE REGISTER 1

MODE REGISTER 2

NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)

NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)

NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)

MODE REGISTER 3

MACROVISION REGISTERS (ADV7175 ONLY)

•

MACROVISION REGISTERS (ADV7175 ONLY)

Figure 30. Subaddress Register

The MPU can write to or read from all of the registers of the

ADV7175/ADV7176 except the subaddress register which is a

write only register. The subaddress register determines which

cations with the part through the bus start with an access to the

subaddress register. Then a read/write operation is performed

from/to the target address which then increments to the next

address until a stop command on the bus is performed.

The following section describes each register, including

subaddress register, mode registers, subcarrier frequency regis-

ters, subcarrier phase register, timing registers, closed captioning

extended data registers, closed captioning data registers and

NTSC pedestal control registers in terms of its configuration.

Subaddress Register (SR7–SR0)

The communications register is an eight bit write-only register.

After the part has been accessed over the bus and a read/write

operation is selected, the subaddress set up. The subaddress

place.

Figure 30 shows the various operations under the control of the

subaddress register. Zero should always be written to SR7–

SR5.

These bits are setup to point to the required starting address.

MODE REGISTER 0 MR0 (MR07–MR00)

(Address (SR4–SR0) = 00H)

Mode Register 0 is a 8-bit wide register.

Figure 31 shows the various operations under the control of

Mode Register 0. This register can be read from as well written to.

MR01

MR00

MR07

MR02

MR04

MR03

MR05

MR06

OUTPUT VIDEO

STANDARD SELECTION

NTSC

PAL (B, D, G, H, I)

PAL (M)

RESERVED

MR01 MR00

MR07

(0)

ZERO SHOULD

BE WRITTEN TO

THIS BIT

OUTPUT SELECT

YC OUTPUT

RGB/YUV OUTPUT

MR06

FILTER SELECT

LOW PASS FILTER (A)

NOTCH FILTER

EXTENDED MODE

LOW PASS FILTER (B)

MR04 MR03

RGB SYNC

DISABLE

ENABLE

MR05

PEDESTAL CONTROL

PEDESTAL OFF

PEDESTAL ON

MR02

Figure 31. Mode Register 0

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