ADV7175 datasheet(20/36 Pages) AD

20 / 36 page

ADV7175/ADV7176

REV. A

–20–

HSYNC

to VSYNC/FIELD Delay Control (TR13–TR12)

These bits adjust the position of the HSYNC output relative to

the FIELD/VSYNC output.

HSYNC

to FIELD Delay Control (TR15–TR14)

When the ADV7175/ADV7176 is in Timing Mode 1, these bits

adjust the position of the HSYNC output relative to the FIELD

output rising edge.

VSYNC

Width (TR15–TR14)

When the ADV7175/ADV7176 is in Timing Mode 2, these bits

adjust the VSYNC pulse width.

HSYNC

to Pixel Data Adjust (TR17–TR16)

This enables the HSYNC to be adjusted with respect to the

pixel data. This allows the Cr and Cb components to be

swapped. This adjustment is available in both master and slave

timing modes.

MODE REGISTER 2 MR2 (MR27–MR20)

(Address (SR4-SR0) = 0DH)

Mode Register 2 is an 8-bit wide register.

Figure 38 shows the various operations under the control of

Mode Register 2. This register can be read from as well written to.

MODE REGISTER 2 (MR27–MR20) BIT DESCRIPTION

Square Pixel Mode Control (MR20)

This bit is used to setup square pixel mode. This is available in

slave mode only. For NTSC, a 24.54 MHz clock must be sup-

plied. For PAL, a 29.5 MHz clock must be supplied.

Genlock Control (MR22–MR21)

These bits control the genlock feature of the ADV7175/

ADV7176 Setting MR21 to a Logic “1” configures the

SCRESET/RTC pin as an input. Setting MR22 to logic level

“0” configures the SCRESET/RTC pin as a subcarrier reset in-

put. Therefore, the subcarrier will reset to Field 0 following a

low to high transition on the SCRESET/RTC pin. Setting

MR22 to Logic Level “1” configures the SCRESET/RTC pin as

a real time control input.

CLOSED CAPTIONING EXTENDED DATA REGISTERS

1–0 (CED15–CED00)

(Address (SR4–SR0) = 09–08H)

These 8-bit wide registers are used to set up the closed

captioning extended data bytes. Figure 35 shows how the high

and low bytes are set up in the registers.

BYTE 1

BYTE 0

CED6

CED5

CED3

CED1

CED4

CED2

CED0

CED7

CED14 CED13

CED11

CED9

CED12

CED10

CED8

CED15

Figure 35. Closed Captioning Extended Data Register

CLOSED CAPTIONING DATA REGISTERS 1–0

(CCD15–CCD00)

(Subaddress (SR4–SR0) = 0B–0AH)

These 8-bit wide registers are used to set up the closed

captioning data bytes. Figure 36 shows how the high and low

bytes are set up in the registers.

BYTE 1

BYTE 0

CCD6

CCD5

CCD3

CCD1

CCD4

CCD2

CCD0

CCD7

CCD14 CCD13

CCD11

CCD9

CCD12

CCD10

CCD8

CCD15

Figure 36. Closed Captioning Data Register

TIMING REGISTER 1 (TR17–TR10)

(Address (SR4–SR0) = 0CH)

Timing Register 1 is an 8-bit wide register.

Figure 37 shows the various operations under the control of

Timing Register 1. This register can be read from as well

written to. This register can be used to adjust the width and

position of the master mode timing signals.

TIMING REGISTER 1 (TR17–TR10) BIT DESCRIPTION

HSYNC

Width (TR11–TR10)

These bits adjust the HSYNC pulse width.

TR11

TR10

TR17

TR12

TR13

TR15

TR16

TR14

HSYNC WIDTH

1 x TPCLK

4 x TPCLK

16 x TPCLK

128 x TPCLK

TR11 TR10

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

Tb + 32µs

TR15 TR14

HSYNC TO PIXEL

DATA ADJUSTMENT

TR17 TR16

0 x TPCLK

1 x TPCLK

2 x TPCLK

3 x TPCLK

HSYNC TO

FIELD/

VSYNC DELAY

TR13 TR12

1 x TPCLK

3 x TPCLK

16 x TPCLK

64 x TPCLK

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

1 x TPCLK

4 x TPCLK

16 x TPCLK

64 x TPCLK

LINE 313

LINE 314

LINE 1

TIMING MODE 1 (MASTER/PAL)

HSYNC

FIELD/

VSYNC

Figure 37. Timing Register 1

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