RT7274 datasheet(20/22 Pages) RICHTEK

20 / 22 page

RT7274/79/80/81

DS7274/79/80/81-01 February 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Layout Consideration

Follow the PCB layout guidelines for optimal performance

of the RT7274/79/80/81

Keep the traces of the main current paths as short and

wide as possible.

Put the input capacitor as close as possible to the device

pins (VIN and GND).

SW node is with high frequency voltage swing and

should be kept at small area. Keep sensitive

components away from the SW node to prevent stray

capacitive noise pickup.

Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the RT7274/79/80/81 FB pin.

The GND and Exposed Pad should be connected to a

strong ground plane for heat sinking and noise protection.

(a). For TSSOP-14 (Exposed Pad) Package

Figure 6. Derating Curve of Maximum Power Dissipation

package, the thermal resistance,

θJA, is 49°C/W on a

standard JEDEC 51-7 four-layer thermal test board. The

maximum power dissipation at TA= 25

°C can be calculated

by the following formulas :

PD(MAX) = (125

°C − 25°C) / (40°C/W) = 2.50W for

TSSOP-14 (Exposed Pad) package

PD(MAX) = (125

°C − 25°C) / (49°C/W) = 2.04W for

SOP-8 (Exposed Pad) package

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curves in Figure 6 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

VIN

PGND

GND

PVCC

PGOOD

PGND

BOOT

VOUT

VINR

PGND

CVCC

CIN

CBOOT

VOUT

COUT

SW should be connected to inductor by

Wide and short trace. Keep sensitive

components away from this trace.

Place the feedback components

as close to the FB as possible

for better regulation.

Place the input and output

capacitors as close to the

IC as possible.

VOUT

PGND

Figure 7. PCB Layout Guide

(b). For SOP-8 (Exposed) Package

PVCC

VIN

BOOT

GND

VOUT

GND

Input capacitor must be placed

as close to the IC as possible.

SW should be connected to inductor by

Wide and short trace. Keep sensitive

components away from this trace.

The resistor divider must

be connected as close to

the device as possible.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

025

100

125

Ambient Temperature (°C)

Four-Layer PCB

SOP-8 (Exposed Pad)

TSSOP-14 (Exposed Pad)

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