REV. A

SSM2165

–7–

Control Circuitry

The output of the rms level detector is a signal proportional to

the log of the true rms value of the buffer output with an added

dc offset. The control circuitry subtracts a dc voltage from this

signal, scales it, and sends the result to the VCA to control the

gain. The VCA’s gain control is logarithmic: a linear change in

control signal causes a dB change in gain. It is this control law

that allows linear processing of the log rms signal to provide the

flat compression characteristic on the input/output characteris-

tic shown in Figure 10.

Compression Ratio

Changing the scaling of the control signal fed to the VCA

causes a change in the circuit’s compression ratio, “r.” This

effect is shown in Figure 14. The compression ratio can be set

by connecting a resistor between the COMP RATIO pin (Pin

6) and GND. Lowering RCOMP gives smaller compression

ratios as indicated in Figure 2, with values of about 5 k

Ω or less

resulting in a compression ratio of 1:1. AGC performance is

achieved with compression ratios between 2:1 and 15:1, and is

dependent on the application. A 200 k

Ω potentiometer may be

used to allow this parameter to be adjusted.

INPUT – dB

15:1

5:1

2:1

1:1

1

1

VCA GAIN

Figure 14. Effect of Varying the Compression Ratio

Rotation Point

An internal dc reference voltage in the control circuitry sets the

rotation point. The rotation point determines the output level

above which limiting occurs. That is, in the limiting region, a

10 dB change of input results in a 1 dB change of output. The

rotation point is set to 40 mV (–26 dBu) for the SSM2165-1

and 100 mV (–18 dBu) for the SSM2165-2. In the SSM2165,

limiting is compression at a fixed compression ratio of approxi-

mately 15:1. The fixed gain in the VCA is 18 dB for the

SSM2165-1 and 8 dB for the SSM2165-2. The output signals

at limiting are, therefore, 320 mV and 250 mV respectively.

These are summarized in Table I.

Maximum Output

Since limiting occurs for signals larger than the rotation point

output signal level. The application will determine which ver-

sion of the SSM2165 should be selected. The output level

should match the maximum input allowed by the following

stage. Occasional larger signal transients will then be attenuated

by the action of the limiter.

Downward Expansion Threshold

The downward expansion threshold, or noise gate, is deter-

mined by a reference voltage internal to the control circuitry.

The noise gate threshold is 500

µV for both versions of the

SSM2165. Users requiring some other noise gate should con-

sider using the SSM2166. High volume users may wish to con-

sider a custom version of the SSM2165 with other noise gate

thresholds or rotation points.

Power-On/Power-Off Settling Time

Cycling the power supply to the SSM2165 will result in quick

settling times: the off-on settling time of the SSM2165 is less

than 200 ms, while the on-off settling time is less than 1 ms.

Note that transients may appear at the output of the device

during power up and power down. A clickless mute function is

available on the SSM2166 only.

PC Board Layout Considerations

Since the SSM2165 is capable of wide bandwidth operation at

high gain, special care must be exercised in the layout of the PC

board which contains the IC and its associated components.

The following applications hints should be considered and/or

followed:

1. In some high system gain applications, the shielding of input

wires to minimize possible feedback from the output of the

SSM2165 back to the input circuit may be necessary.

2. A single-point (“star”) ground implementation is recom-

mended in addition to maintaining short lead lengths and

PC board runs. In systems where an analog ground and a

digital ground are available, the SSM2165 and its surround-

ing circuitry should be connected to the analog ground.

Wire-wrap board connections and grounding implementa-

tions are to be explicitly avoided.

3. The internal buffer of the SSM2165 was designed to drive

only the input of the internal VCA and its own feedback

network. Stray capacitive loading to ground from either Pin

3 or Pin 2 in excess of 5 pF to 10 pF can cause excessive

phase shift and can lead to circuit instability.

4. When using high impedance sources, it can be advantageous

to shunt the source with a capacitor to ground at the input

pin of the IC (Pin 4) to lower the source impedance at high

frequencies, as shown in Figure 15. A capacitor with a value

of 1000 pF is a good starting value and sets a low pass corner

at 31 kHz for 5 k

Ω sources.

1000pF

C1

0.1 F

AUDIO IN

4

+IN

SSM2165

NOTE: ADDITIONAL CIRCUIT DETAILS

OMITTED FOR CLARITY.

Figure 15. Circuit Configuration for Use with High

Impedance Signal Sources