ORLI10G datasheet(46/72 Pages) AGERE

46 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Pin Information (continued)

In Figure 18, an output refers to a signal flowing into the FGPA logic (out of the embedded core) and an input refers

to a signal flowing out of the FPGA logic (into the embedded core).

Table 18. Embedded Core/FPGA Interface Signal Description

Pin Name

I/O

Description

Receive Signals

RX_DAT_OUT<127:0>

Data from demultiplexer on receive side.

RX_CLK8_OUT<3:0>

Divided down clocks on receive side.

RX_ENB8_OUT<3:0>

Data enables on receive side.

RX1_VCOP

RX1_PLL output clock on receive side (M/N clock) after phase select.

RX1_VCO

RX1_PLL output clock on receive side (M/N clock) before phase select.

RX2_VCOP

RX2_PLL output clock on receive side (x1 clock) after phase select.

RX2_VCO

RX2_PLL output clock on receive side (x1 clock) before phase select.

RX2_FBCKI

PLL feedback input to RX2_PLL. This allows for the removal of the

FPGA clock routing delay.

RX1_BYPASS

Set to 1 to bypass the RX1 PLL.

RX2_BYPASS

Set to 1 to bypass the RX2 PLL.

RX_LOCK

Lock signal for RX1_PLL and RX2_PLL. This signal is a logical OR of

the lock signal from both PLLs. It is not integrated; thus, small glitches

can occur on this signal during normal PLL operation.

Transmit Signals

TX_DAT_IN<127:0>

Data to multiplexer on transmit side.

TX_CLK8_IN<3:0>

Clocks to multiplexer on transmit side.

TX_ENB8_IN[3:0]

Data enables on transmit side.

TX1_VCOP

TX1_PLL output clock on transmit side (M/N clock) after phase select.

TX1_VCO

TX1_PLL output clock on transmit side (M/N clock) before phase select.

TX2_VCOP

TX2_PLL output clock on transmit side (x1 clock) after phase select.

TX2_VCO

TX2_PLL output clock on transmit side (x1 clock) before phase select.

TX2_FBCKI

PLL feedback input to TX2 PLL. This allows for the removal of the

FPGA clock routing delay.

TX1_BYPASS

Set to 1 to bypass the TX1 PLL.

TX2_BYPASS

Set to 1 to bypass the TX2 PLL.

TX_LOCK

Lock signal for TX1_PLL and TX2_PLL. This signal is a logical OR of

the lock signal from both PLLs. It is not integrated; thus, small glitches

can occur on this signal during normal PLL operation.

Vss_A<7:4>

—

Analog ground for the embedded line interface PLLs.

VDD33_A<7:4>

—

Analog power supply for the embedded line interface PLLs.

ORLI10G Datasheet(PDF) 46 Page - Agere Systems

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