L9758 datasheet(16/29 Pages) STMICROELECTRONICS

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Electrical characteristics

L9758

16/29

Doc ID 14273 Rev 3

4.6

VCORE linear regulator

Tamb = -40 °C to 125 °C, VBAT= VBAT_SW = 5.5 to 26.5 V, unless otherwise specified.

VDDL_MAX

Maximum

overshoot

5 mA <IDDL < 1 A, VPROG3 = Open

4.0 V < VBAT_SW < 18 V

ΔVB/Δt < 70 V/ms

5 mA < IDDL < 1 A, VPROG3 = Low

4.0 V < VBAT_SW < 18 V

ΔVB/Δt < 70 V/ms

3.75

3.6

ΔV

DDL/Δt

Output voltage slew

rate at power-up

5 mA <IDDL < 1 A VBAT_SW =13.5 V

V/ms

IDDL

Load current

1000

VDDLlineR

Line regulation

5.5 V < VBAT_SW < 7 V

-8

VDDLloadR

Load regulation

5 mA < IDDL< 1 A

-8

Table 11.

VDDL linear regulator (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Table 12.

VCORE linear regulator

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VCORE

Output voltage

5mA < ICORE < 1A 4.0V < VBAT_SW < 18V

1.47

1.53

CddL

ESR

Output capacitor

Ceramic or Tantalum

4.70

100

160

µF

RRddL

Ripple rejection

F= 375 kHz

VCORE_M

Maximum

overshoot

5 mA < ICORE < 1 A

4.0 V < VBAT_SW < 18 V

1.7

ΔV

CORE/Δt

Output voltage slew

rate at power-up

5 mA < ICORE < 1 A VBAT_SW=13.5 V

V/ms

ICORE

Load current

1000

VCORE_PROG

Range of

programmability

Using external resistor divider

1.05

1.5

2.8

VCORE_FBK

Feedback voltage

0.98

1.02

VCORElineR

Line regulation

5.5 V < VBAT_SW < 7 V

-25

+25

VCOREloadR

Load regulation

5 mA < ICORE < 1 A

-25

+25

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