ISL70001ASEH

17

FN8365.0

May 22, 2013

Another consideration in selecting the output capacitors is loop

stability. The total output capacitance sets the dominant pole of

the PWM. Because the ISL70001ASEH uses integrated

compensation techniques, it is necessary to restrict the output

capacitance in order to optimize loop stability. The

recommended load capacitance can be estimated using

Equation 13.

Another stability requirement on the selection of the output

90kHz. This range is set by an internal, single compensation zero

at 8.6kHz. This ESR zero location contributes to increased phase

margin of the control loop; therefore if a capacitor is chosen with

an inadequate ESR stability may be compromised. Equation 14

maybe be used to calculate the required ESR to place the ‘ESR

zero’ in the recommended range:

In conclusion, the output capacitors must meet three criteria:

1. They must have sufficient bulk capacitance to sustain the

output voltage during a load transient while the output

inductor current is slewing to the value of the load transient.

2. The ESR must be sufficiently low to meet the desired output

voltage ripple due to the output inductor current.

3. The ESR zero should be placed, in a rather large range, to

provide additional phase margin.

OUTPUT INDUCTOR SELECTION

Once the output capacitors are selected, the maximum allowable

inductance as shown in Equation 15.

Since the output capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the transient,

the capacitor voltage becomes slightly depleted. The output

inductor must be capable of assuming the entire load current

before the output voltage decreases more than

places an upper limit on inductance.

Equation 16 gives the upper limit on output inductance for the

case when the trailing edge of the current transient causes a

greater output voltage deviation than the leading edge.

Equation 17 addresses the leading edge. Normally, the trailing

edge dictates the inductance selection because duty cycles are

usually <50%. Nevertheless, both inequalities should be

evaluated, and inductance should be governed based on the

the peak-to-peak ripple current in the output inductor.

The other concern when selecting an output inductor is to ensure

there is adequate slope compensation when the regulator is

operated above 50% duty cycle. Since the internal slope

compensation is fixed, output inductance should satisfy

Equation 18 to ensure this requirement is met.

Input Capacitor Selection

Input capacitors are responsible for sourcing the AC component

of the input current flowing into the switching power devices.

Their RMS current capacity must be sufficient to handle the AC

component of the current drawn by the switching power devices,

which is related to duty cycle. The maximum RMS current

required by the regulator is closely approximated by Equation 19.

The important parameters to consider when selecting an input

capacitor are the voltage rating and the RMS ripple current

rating. For reliable operation, select capacitors with voltage

ratings at least 1.5x greater than the maximum input voltage.

The capacitor RMS ripple current rating should be higher than

the largest RMS ripple current required by the circuit.

Ceramic capacitors with X7R dielectric are recommended.

Alternately, a combination of low ESR solid tantalum capacitors

and ceramic capacitors with X7R dielectric may be used. The

ISL70001ASEH requires a minimum effective input capacitance

of 100µF for stable operation.

Derating Current Capability

Most space programs issue specific derating guidelines for parts,

but these guidelines take the pedigree of the part into account.

For instance, a device built to MIL-PRF-38535, such as the

ISL70001ASSEH, is already heavily derated from a current

density standpoint. However, a mil-temp or commercial IC that is

up-screened for use in space applications may need additional

current derating to ensure reliable operation because it was not

built to the same standards as the ISL70001ASEH.

Figure 26 shows the maximum average output current of the

ISL70001ASEH with respect to junction temperature. These plots

take into account the worst-case current share mismatch in the

power blocks and the current density requirement of MIL-PRF-

ISL70001ASEH can handle 12.1A at +125°C from a worst-case

current density standpoint, but the part is limited to 7.8A

75

μF NumberofLXxPinsConnected 1.8V

-------------

×

×

=

(EQ. 13)

ESR

1

2

π f

ZESR

() C

OUT

()

----------------------------------------------

=

(EQ. 14)

–

()V

OUT

×

×

--------------------------------------------------

×

≥

(EQ. 15)

2

⋅⋅

---------------------------------------

ΔV

MAX

⋅

()

–

≤

(EQ. 16)

⋅

--------------------------

ΔV

MAX

ΔI

⋅

()

–

V

IN

V

O

UT

–

⎝⎠

⎛⎞

≤

(EQ. 17)

4.32

μH

NumberofLXxPinsConnected

-----------------------------------------------------------------------------------

≥

(EQ. 18)

IRMS

MAX

VOUT

VIN

-----------------

IOUT

MAX

2

1

12

------

VIN VOUT

–

×

----------------------------------

VOUT

VIN

-----------------

×

⎝⎠

⎜⎟

⎛⎞ 2

×

+

⎝⎠

⎜⎟

⎛⎞

×

=

(EQ. 19)