ADF4159CCPZ datasheet(32/36 Pages) AD

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ADF4159

Data Sheet

Rev. B | Page 32 of 36

FAST LOCK MODE

The ADF4159 can operate in fast lock mode. In this mode, the

charge pump current is boosted and additional resistors are

connected to maintain the stability of the loop.

Fast Lock Timer and Register Sequences

If the fast lock mode is used, a timer value must be loaded into

the PLL to determine the time spent in wide bandwidth mode.

When Bits DB[20:19] in Register R4 are set to 01 (fast lock

divider), the timer value is loaded via the 12-bit clock divider

value. Before fast lock is enabled, the initialization sequence

must be performed after the part is first powered up (see the

Initialization Sequence section). Note that the fast lock feature

does not work in ramp mode.

To use fast lock, the PLL must be written to in the following

sequence:

1. Set Bits DB[20:19] = 01 in Register R4 and set the fast lock

timer value (Bits DB[18:7]).

2. If a longer time in wide loop bandwidth is required, set the

CLK1 divider value (Bits DB[14:3]) in Register R2.

Note that the length of time that the PLL remains in wide band-

width mode is equal to CLK1 × fast lock timer/fPFD, where CLK1

is the 12-bit CLK1 divider programmed in Register R2.

Fast Lock Example

In this example, the PLL has a reference frequency of 13 MHz

(fPFD = 13 MHz) and a required lock time of 50 µs with CLK1 = 10

(12-bit CLK1 divider in Register R2). In this case, the PLL is set

to wide bandwidth mode for 40 µs.

If the time period set for wide bandwidth mode is 40 µs, then

Fast Lock Timer Value = Time in Wide Bandwidth × fPFD/CLK1

Fast Lock Timer Value = 40 µs × 13 MHz/10 = 52.

Therefore, 52 must be loaded into the clock divider value

in Register R4 (Step 1 in the Fast Lock Timer and Register

Sequences section).

Fast Lock Loop Filter Topology

To use fast lock mode, an extra connection from the PLL to the

loop filter is needed. The damping resistor in the loop filter must

be reduced to ¼ of its value in wide bandwidth mode. This reduc-

tion is required because the charge pump current is increased

by 16 in wide bandwidth mode, and stability must be ensured.

To further enhance stability and mitigate frequency overshoot

during a frequency change in wide bandwidth mode, Resistor R3

is connected (see Figure 52). During fast lock, the SW1 pin is

shorted to ground, and the SW2 pin is connected to CP (set

Bits DB[20:19] in Register R4 to 01 for fast lock divider).

The following two topologies can be used:

•

Divide the damping resistor (R1) into two values (R1 and

R1A) that have a ratio of 1:3 (see Figure 52).

•

Connect an extra resistor (R1A) directly from SW1 (see

Figure 53). The extra resistor must be selected such that the

parallel combination of an extra resistor and the damping

resistor (R1) is reduced to ¼ of the original value of R1.

For both topologies, the ratio R3:R2 must equal 1:4.

ADF4159

SW2

SW1

R1A

VCO

Figure 52. Fast Lock Loop Filter Topology 1

ADF4159

SW2

SW1

R1A

VCO

Figure 53. Fast Lock Loop Filter Topology 2

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