Data Sheet

ADF4159

Rev. B | Page 23 of 36

DELAY REGISTER (R7) MAP

When Bits DB[2:0] are set to 111, the on-chip delay register

(Register R7) is programmed (see Figure 32).

Reserved Bits

All reserved bits must be set to 0 for normal operation.

When Bit DB23 is set to 0, there is no delay before the start of

is set to 1, a delay is enabled before the start of the ramp if the

delayed start is enabled via Bit DB15.

Triangular Delay

When Bit DB22 is set to 1, a delay is enabled between each

section of a triangular ramp, resulting in a clipped ramp. This

setting works only for triangular ramps and when the ramp

delay is activated. When Bit DB22 is set to 0, the delay between

triangular ramps is disabled.

Single Full Triangle

When Bit DB21 is set to 1, the single full triangle function is

enabled. When Bit DB21 is set to 0, this function is disabled.

For more information, see the Waveform Generation section.

ramp. When Bit DB20 is set to 0, this function is disabled.

Fast Ramp

When Bit DB19 is set to 1, the triangular waveform is activated

with two different slopes. This waveform can be used as an alter-

native to the sawtooth ramp because it mitigates the overshoot

at the end of the ramp in a waveform. Fast ramp is achieved by

changing the top frequency to the bottom frequency in a series of

small steps instead of one big step. When Bit DB19 is set to 0, the

fast ramp function is disabled (see the Fast Ramp Mode section).

Ramp Delay Fast Lock

When Bit DB18 is set to 1, the ramp delay fast lock function is

enabled. When Bit DB18 is set to 0, this function is disabled.

Ramp Delay

When Bit DB17 is set to 1, the delay between ramps function is

enabled. When Bit DB17 is set to 0, this function is disabled.

Delay Clock Select

When Bit DB16 is set to 0, the PFD clock is selected as the delay

Delayed Start Enable

When Bit DB15 is set to 1, the delayed start is enabled. When

Bit DB15 is set to 0, the delayed start is disabled.

12-Bit Delay Start Word

Bits DB[14:3] determine the delay start word. The delay start

word affects the duration of the ramp start delay.

DB31

12-BIT DELAY START WORD

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

TD1

ST1

TR1

FR1

RD1

DC1 DSE1 DS12 DS11 DS10 DS9

DS8

DS7

DS6

DS5

C3(1) C2(1) C1(1)

DS12 DS11

...

DS2

DS1

DELAY START WORD

0

0

...

0

0

0

0

0

...

0

1

1

0

0

...

1

0

2

0

0

...

1

1

3

.

.

...

.

.

.

.

.

...

.

.

.

.

.

...

.

.

.

1

1

...

0

0

4092

1

1

...

0

1

4093

1

1

...

1

0

4094

1

1

...

1

1

4095

DS4

DS3

DS1

DS2

DSE1 DEL START EN

0

DISABLED

1

ENABLED

DC1

DEL CLK SEL

0

PFD CLK

1

RD1

RAMP DELAY

FR1

FAST RAMP

ST1

SING FULL TRI

0

DISABLED

1

ENABLED

0

DISABLED

1

0

1

ENABLED

0

DISABLED

1

ENABLED

DISABLED

ENABLED

0

RAMP DELAY FL

0

1

DISABLED

ENABLED

0

0

1

DISABLED

ENABLED

TD1 TRI DELAY

0

DISABLED

1

ENABLED

CONTROL

BITS

Figure 32. Delay Register (R7) Map