MCP79411 datasheet(5/60 Pages) MICROCHIP

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 2010-2013 Microchip Technology Inc.

DS20002266E-page 5

MCP79410/MCP79411/MCP79412

TABLE 1-2:

AC CHARACTERISTICS

Electrical Characteristics:

Industrial (I):

VCC = +1.8V to 5.5V

TA = -40°C to +85°C

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

1FCLK

Clock frequency

—

100

400

kHz

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

2THIGH

Clock high time

4000

600

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

3TLOW

Clock low time

4700

1300

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

4TR

SDA and SCL rise time

(Note 1)

—

1000

300

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

5TF

SDA and SCL fall time

(Note 1)

—

1000

300

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

6THD:STA Start condition hold time

4000

600

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

7TSU:STA

Start condition setup time

4700

600

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

8THD:DAT Data input hold time

—

(Note 4)

9TSU:DAT Data input setup time

250

100

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

TSU:STO Stop condition setup time

4000

600

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

TAA

Output valid from clock

—

3500

900

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

TBUF

Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

—

1.8V

 VCC < 2.5V

2.5V

 VCC  5.5V

TSP

Input filter spike suppression

(SDA and SCL pins)

—50

(Note 1 and Note 2)

TWC

Write cycle time (byte or

page)

—5

—

Endurance

—

cycles 25°C, VCC = 5.5V Page mode

(Note 3)

TOSF

OSCON Time out

(Note 5)

TFVCC

VCC Fall Time

300

sFrom VTRIP (max) to VTRIP (min)

(Note 1)

TRVCC

VCC Rise Time

sFrom VTRIP (min) to VTRIP (max)

(Note 1)

FXTAL

Crystal Frequency

32.768

kHz

Note 1: Not 100% tested.

2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression.

3: This parameter is not tested but ensured by characterization.

4: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300ns) of the falling edge of the SCL to avoid unintended generation of Start or Stop conditions.

Parameter is not tested, ensured by characterization.

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