QG5000XSL9TH datasheet(6/458 Pages) INTEL

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

5.3.4

Data Poisoning in Memory...................................................................... 314

5.3.5

Patrol Scrubbing ................................................................................... 314

5.3.6

Demand Scrubbing ............................................................................... 315

5.3.7

x8 Correction ....................................................................................... 315

5.3.8

Single Device Data Correction (SDDC) Support ......................................... 316

5.3.9

FB-DIMM Memory Configuration Mechanism ............................................. 316

5.3.10 FB-DIMM Memory Failure Isolation Mechanisms ........................................ 318

5.3.11 DDR2 Protocol...................................................................................... 322

5.3.12 Memory Thermal Management................................................................ 322

5.3.13 Electrical Throttling ............................................................................... 333

5.4

Behavior on Overtemp State in AMB................................................................... 333

5.5

Interrupts....................................................................................................... 334

5.6

XAPIC Interrupt Message Delivery...................................................................... 334

5.6.1

XAPIC Interrupt Message Format ............................................................ 334

5.6.2

XAPIC Destination Modes ....................................................................... 335

5.6.3

Interrupt Redirection............................................................................. 336

5.6.4

EOI..................................................................................................... 338

5.7

I/O Interrupts ................................................................................................. 338

5.7.1

Ordering.............................................................................................. 338

5.7.2

Hardware IRQ IOxAPIC Interrupts........................................................... 339

5.7.3

Message Signalled Interrupts ................................................................. 339

5.7.4

Non-MSI Interrupts - “Fake MSI” ............................................................ 339

5.8

Interprocessor Interrupts (IPIs) ......................................................................... 340

5.9

Chipset Generated Interrupts ............................................................................ 342

5.9.1

Intel 5000X Chipset Generation of MSIs.................................................. 344

5.10 Legacy/8259 Interrupts .................................................................................... 346

5.11 Interrupt Error Handling ................................................................................... 346

5.12 Enterprise South Bridge Interface (ESI) .............................................................. 347

5.12.1 Power Management Support................................................................... 348

5.12.2 Special Interrupt Support....................................................................... 348

5.12.3 Inbound Interrupts ............................................................................... 348

5.12.4 Legacy Interrupt Messages .................................................................... 349

5.12.5 End-of-Interrupt (EOI) Support .............................................................. 349

5.12.6 Error Handling...................................................................................... 349

5.13 PCI Express Ports ............................................................................................ 349

5.13.1 Intel 5000X Chipset MCH PCI Express Port Overview ................................ 350

5.13.2 Enterprise South Bridge Interface (ESI) ................................................... 351

5.13.3 PCI Express Ports 2 and 3 ...................................................................... 351

5.13.4 PCI Express General Purpose Ports.......................................................... 352

5.13.5 Supported Length Width Port Partitioning................................................. 353

5.13.6 PCI Express Port Support Summary ........................................................ 354

5.13.7 PCI Express Port Physical Layer Characteristics ......................................... 355

5.13.8 Link Layer............................................................................................ 357

5.13.9 Flow Control......................................................................................... 359

5.13.10Transaction Layer ................................................................................. 361

5.14 Power Management.......................................................................................... 361

5.14.1 Supported ACPI States .......................................................................... 361

5.14.2 FB-DIMM Thermal Management .............................................................. 362

5.14.3 FB-DIMM Thermal Diode Overview .......................................................... 362

5.15 System Reset.................................................................................................. 362

5.15.1 MCH Power Sequencing ......................................................................... 362

5.15.2 MCH Reset Types.................................................................................. 363

5.15.3 Targeted Reset Mechanism .................................................................... 364

5.15.4 BINIT# Mechanism ............................................................................... 365

5.15.5 Reset Sequencing ................................................................................. 365

5.16 SMBus Interfaces Description ............................................................................ 366

QG5000XSL9TH Datasheet(PDF) 6 Page - Intel Corporation

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