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16C84 Datasheet(PDF) 45 Page - Microchip Technology |
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16C84 Datasheet(HTML) 45 Page - Microchip Technology |
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45 / 110 page  PIC16C84 1996-2013 Microchip Technology Inc. DS30445D-page 45 FIGURE 8-15: INTERRUPT LOGIC FIGURE 8-16: INT PIN INTERRUPT TIMING RBIF RBIE T0IF T0IE INTF INTE GIE EEIE Wake-up (If in SLEEP mode) Interrupt to CPU EEIF Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 OSC1 CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed Interrupt Latency PC PC+1 PC+1 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (PC) Inst (PC+1) Inst (PC-1) Inst (0004h) Dummy Cycle Inst (PC) — 1 4 5 1 Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. 2 3 |
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