PIC16CE623 datasheet(44/114 Pages) MICROCHIP

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PIC16CE62X

DS40182D-page 44

 1998-2013 Microchip Technology Inc.

8.4

Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal refer-

ence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs, otherwise the maximum delay of

the comparators should be used (Table 13-1 ).

8.5

Comparator Outputs

The comparator outputs are read through the CMCON

outputs may also be directly output to the RA3 and RA4

I/O pins. When the CM<2:0> = 110, multiplexors in the

output path of the RA3 and RA4 pins will switch and the

output of each pin will be the unsynchronized output of

the comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the

response

time

given

the

specifications.

Figure 8-3 shows the comparator output block diagram.

The TRISA bits will still function as an output

enable/disable for the RA3 and RA4 pins while in this

mode.

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as

a ‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

2: Analog levels on any pin that is defined

as a digital input may cause the input

buffer to consume more current than is

specified.

FIGURE 8-3:

COMPARATOR OUTPUT BLOCK DIAGRAM

To RA3 or

RA4 Pin

Data

Bus

RD CMCON

Set

MULTIPLEX

CMIF

Bit

Port Pins

RD CMCON

NRESET

From

Other

Comparator

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