PIC24F32KA302 datasheet(38/364 Pages) MICROCHIP

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DS39995D-page 38

PIC24FV32KA304 FAMILY

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® MCU

devices and improve data space memory usage

efficiency, the PIC24F instruction set supports both

word and byte operations. As a consequence of byte

accessibility, all Effective Address (EA) calculations are

internally scaled to step through word-aligned memory.

For example, the core recognizes that Post-Modified

a value of Ws + 1 for byte operations and Ws + 2 for

word operations.

Data byte reads will read the complete word, which

contains the byte, using the LSB of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the data path. That is, data

memory and the registers are organized as two

parallel, byte-wide entities with shared (word) address

decode, but separate write lines. Data byte writes only

write to the corresponding side of the array or register,

which matches the byte address.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed, but the write

will not occur. In either case, a trap is then executed,

allowing the system and/or user to examine the

machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the

LSB; the MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow the

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

4.2.3

NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is

referred to as the Near Data Space (NDS). Locations in

this space are directly addressable via a 13-bit abso-

lute address field within all memory direct instructions.

The remainder of the data space is addressable

indirectly. Additionally, the whole data space is

addressable using MOV instructions, which support

Memory Direct Addressing (MDA) with a 16-bit address

field. For PIC24FV32KA304 family devices, the entire

implemented data memory lies in Near Data Space.

4.2.4

SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24F core

and peripheral modules for controlling the operation of

the device.

SFRs are distributed among the modules that they

control and are generally grouped together by the

module. Much of the SFR space contains unused

addresses; these are read as ‘0’. The SFR space,

where the SFRs are actually implemented, is provided

in Table 4-2. Each implemented area indicates a

32-byte region, where at least one address is

implemented as an SFR. A complete listing of

implemented SFRs, including their addresses, is

provided in Table 4-3 through Table 4-25.

TABLE 4-2:

IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00

xx20

xx40

xx60

xx80

xxA0

xxC0

xxE0

000h

Core

ICN

Interrupts

—

100h

Timers

Capture

—Compare

—

200h

I2C™

UART

SPI

—

—I/O

300h

A/D/CMTU

—

400h

—

500h

—

600h

—

RTC/Comp

CRC

—

700h

—

System/DS/HLVD

NVM/PMD

—

Legend: — = No implemented SFRs in this block.

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