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PIC24F32KA302 Datasheet(PDF) 142 Page - Microchip Technology |
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PIC24F32KA302 Datasheet(HTML) 142 Page - Microchip Technology |
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142 / 364 page ![]() PIC24FV32KA304 FAMILY DS39995D-page 142 2011-2013 Microchip Technology Inc. FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TMR3 TMR2 Set T3IF (T5IF) Equal Comparator Reset LSB MSB Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. 2: The A/D event trigger is available only on Timer2/3 and Timer4/5 in 32-bit mode, and Timer3 and Timer5 in 16-bit mode. Data Bus<15:0> TMR3HLD Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 16 16 Q QD CK TGATE 0 1 TON TCKPS<1:0> 2 TCY TCS TGATE T2CK A/D Event Trigger(2) (T4CK) (TMR5HLD) (TMR5) (TMR4) Prescaler 1, 8, 64, 256 Gate Sync PR3 PR2 (PR5) (PR4) Sync |
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