PIC24F32KA302 datasheet(174/364 Pages) MICROCHIP

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PIC24FV32KA304 FAMILY

DS39995D-page 174

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I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC

U-0

R/C-0, HS

R-0, HSC

ACKSTAT

TRSTAT

—

BCL

GCSTAT

ADD10

bit 15

bit 8

R/C-0, HS R/C-0, HS

R-0, HSC R/C-0, HSC R/C-0, HSC

R-0, HSC

IWCOL

I2COV

D/A

R/W

RBF

TBF

bit 7

bit 0

Legend:

C = Clearable bit

HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ACKSTAT: Acknowledge Status bit

1 = NACK was detected last

0 = ACK was detected last

Hardware is set or clear at the end of Acknowledge.

bit 14

TRSTAT: Transmit Status bit

(when operating as I2C master; applicable to master transmit operation)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware is set at the beginning of the master transmission; hardware is clear at the end of slave Acknowledge.

bit 13-11

Unimplemented: Read as ‘0’

bit 10

BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during a master operation

0 = No collision

Hardware is set at the detection of a bus collision.

bit 9

GCSTAT: General Call Status bit

1 = General call address was received

0 = General call address was not received

Hardware is set when an address matches the general call address; hardware is clear at Stop detection.

bit 8

ADD10: 10-Bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware is set at a match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection.

bit 7

IWCOL: I2Cx Write Collision Detect bit

1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy

0 = No collision

Hardware is set at an occurrence of a write to I2CxTRN while busy (cleared by software).

bit 6

I2COV: I2Cx Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte

0 = No overflow

Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5

D/A: Data/Address bit (when operating as I2C slave)

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was the device address

Hardware is clear at a device address match; hardware is set by a write to I2CxTRN or by reception of a

slave byte.

PIC24F32KA302 Datasheet(PDF) 174 Page - Microchip Technology

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