ST10R167-Q3 datasheet(8/63 Pages) STMICROELECTRONICS

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ST10R167

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WR/WRL

External Memory Write Strobe. In WR-mode this pin is activated for every

external data write access. In WRL-mode this pin is activated for low byte

data write accesses on a 16-bit bus, and for every data write access on an

8-bit bus. See WRCFG in register SYSCON for mode selection.

READY/READY

Ready Input. The active level is programmable. When the Ready function

is enabled, the selected inactive level at this pin during an external mem-

ory access will force the insertion of memory cycle time waitstates until

the pin returns to the selected active level.

ALE

Address Latch Enable Output. Can be used for latching the address into

external memory or an address latch in the multiplexed bus modes.

External Access Enable pin. A low level at this pin during and after Reset

forces the ST10R167 to begin instruction execution out of external mem-

ory. A high level forces execution out of the internal Flash Memory.

P0L.0 - P0L.7

P0H.0

P0H.1 - P0H.7

100 - 107

108

111 - 117

I/O

Port 0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is

bit-wise programmable for input or output via direction bits. For a pin con-

figured as input, the output driver is put into high-impedance state. In case

of an external bus configuration, Port 0 serves as the address (A) and

address/data (AD) bus in multiplexed bus modes and as the data (D) bus

in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width : 8-bit

16-bit

P0L.0 – P0L.7

: D0 – D7

D0 - D7

P0H.0 – P0H.7

: I/O

D8 - D15

Multiplexed bus modes:

Data Path Width : 8-bit

16-bit

P0L.0 – P0L.7

: AD0 – AD7

AD0 - AD7

P0H.0 – P0H.7

: A8 - A15

AD8 - AD15

P1L.0 - P1L.7

P1H.0 - P1H.7

118 - 125

128 - 135

I/O

Port 1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is

bit-wise programmable for input or output via direction bits. For a pin con-

figured as input, the output driver is put into high-impedance state. Port 1

is used as the 16-bit address bus (A) in demultiplexed bus modes and

also after switching from a demultiplexed bus mode to a multiplexed bus

mode.

The following PORT1 pins also serve for alternate functions:

132

133

134

135

P1H.4

CC24IO

CAPCOM2: CC24 Capture Input

P1H.5

CC25IO

CAPCOM2: CC25 Capture Input

P1H.6

CC26IO

CAPCOM2: CC26 Capture Input

P1H.7

CC27IO

CAPCOM2: CC27 Capture Input

XTAL1

138

Input to the oscillator amplifier and input to the internal clock generator

XTAL2

137

Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1, while leaving

XTAL2 unconnected. Minimum and maximum high/low and rise/fall times

specified in the AC Characteristics must be observed.

RSTIN

140

Reset Input with Schmitt-Trigger characteristics. A low level at this pin for

a specified duration while the oscillator is running resets the ST10R167.

An internal pullup resistor permits power-on reset using only a capacitor

connected to VSS.

In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON

sequence.

Table 1 : Pin list (continued)

Symbol

Type

Function

II - PIN DATA (continued)

ST10R167-Q3 Datasheet(PDF) 8 Page - STMicroelectronics

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