AD7846APZ datasheet(12/24 Pages) AD

12 / 24 page

AD7846

Rev. G | Page 12 of 24

VREF+

VREF–

DAC1

SEGMENT 1

SEGMENT 16

S15

S17

S16

S14

DAC2

DAC3

12-BIT DAC

DB11 TO DB0

DB15 TO DB12

VOUT

RIN

Figure 21. Digital-to-Analog Conversion

OUTPUT STAGE

The output stage of the AD7846 is shown in Figure 22. It is capable

of driving a 2 kΩ/1000 pF load. It also has a resistor feedback

network that allows the user to configure it for gains of 1 or 2.

Table 6 shows the different output ranges that are possible.

An additional feature is that the output buffer is configured as a

track-and-hold amplifier. Although normally tracking its input,

this amplifier is placed in a hold mode for approximately 2.5 μs

after the leading edge of LDAC. This short state keeps the DAC

output at its previous voltage while the AD7846 is internally

changing to its new value. Thus, any glitches that occur in the

transition are not seen at the output. In systems where the

LDAC is tied permanently low, the deglitching is not in

operation.

and

show the outputs of the

AD7846 without and with the deglitcher.

Figure 13

Figure 14

LDAC

VOUT

RIN

DAC3

ONE

SHOT

10kΩ

Figure 22. Output Stage

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