AD7846APZ datasheet(14/24 Pages) AD

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AD7846

Rev. G | Page 14 of 24

BIPOLAR OPERATION

Figure 24 shows the AD7846 set up for ±10 V bipolar operation.

The AD588 provides precision ±5 V tracking outputs that are

fed to the VREF+ and VREF− inputs of the AD7846. The code table

for Figure 24 is shown in Table 9.

DGND

+15V

+5V

VDD

VSS

VCC

VOUT

RIN

VREF+

VREF–

10kΩ

1µF

SIGNAL

GROUND

–15V

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7846*

AD588

VOUT

(–10V TO +10V)

+15V

–15V

100kΩ

39kΩ

+15V

Figure 24. Bipolar ±10 V Operation

Table 9. Offset Binary Code Table for Figure 24

Binary Number in DAC Latch

MSB

LSB1

Analog Output (VOUT)

1111 1111 1111 1111

+10 (32,767/32,768) V

1000 0000 0000 0001

+10 (1/32,768) V

1000 0000 0000 0000

0 V

0111 1111 1111 1111

−10 (1/32,768) V

0000 0000 0000 0000

−10 (32,768/32,768) V

1 LSB = 10 V/215 = 10 V/32,768 = 305 μV.

Full-scale and bipolar zero adjustment are provided by varying

the gain and balance on the AD588. R2 varies the gain on the

AD588 while R3 adjusts the +5 V and −5 V outputs together

with respect to ground.

For bipolar zero adjustment on the AD7846, load the DAC with

100…000 and adjust R3 until VOUT = 0 V. Full scale is adjusted

by loading the DAC with all 1s and adjusting R2 until VOUT =

9.999694 V.

When bipolar zero and full-scale adjustment are not needed, R2

and R3 can be omitted, Pin 12 on the AD588 should be connected

to Pin 11, and Pin 5 should be left floating. If a user wants a 5 V

output range, there are two choices. By tying Pin 6 (RIN) of the

AD7846 to VOUT (Pin 5), the output stage gain is reduced to

unity and the output range is ±5 V. If only a positive 5 V reference

is available, bipolar ±5 V operation is still possible. Tie VREF− to

0 V and connect RIN to VREF+. This also gives a ±5 V output

range. However, the linearity, gain, and offset error specifications

are the same as the unipolar 0 V to 5 V range.

MULTIPLYING OPERATION

The AD7846 is a full multiplying DAC. To obtain four-quadrant

multiplication, tie VREF− to 0 V, apply the ac input to VREF+, and

tie RIN to VREF+. Figure 11 shows the large signal frequency

response when the DAC is used in this fashion.

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