AD9776-EB datasheet(35/56 Pages) AD

35 / 56 page

AD9776/AD9778/AD9779

Rev. A | Page 35 of 56

INTERPOLATION FILTER MINIMUM AND

MAXIMUM BANDWIDTH SPECIFICATIONS

The AD977x uses a novel interpolation filter architecture that

allows DAC IF frequencies to be generated anywhere in the

spectrum. Figure 68 shows the traditional choice of DAC IF

output bandwidth placement. Note that there are no possible

filter modes in which the carrier can be placed near 0.5 × fDATA,

1.5 × fDATA, 2.5 × fDATA, and so on.

–80

–4

fOUT (× Input Data Rate),

ASSUMING 8

× INTERPOLATION

–10

–20

–30

–40

–50

–60

–70

–3

–2

–1

0123

Figure 68. Traditional Bandwidth Options for TxDAC Output IF

The filter architecture not only allows the interpolation filter

pass bands to be centered in the middle of the input Nyquist

zones (as explained in this section), but also allows the possi-

bility of a 3 × fDAC/8 modulation mode. With all of these filter

combinations, a carrier of given bandwidth can be placed

anywhere in the spectrum and fall into a possible pass band of

the interpolation filters. The possible bandwidths accessible

with the filter architecture are shown in Figure 69 and

Figure 70. Note that the shifted and nonshifted filter modes

are all accessible by programming the filter mode for the

particular interpolation rate.

–80

–4

fOUT (× Input Data Rate),

ASSUMING 8× INTERPOLATION

–10

–20

–30

–40

–50

–60

–70

–3

–2

–1

Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture

–80

–4

fOUT (× Input Data Rate),

ASSUMING 8

× INTERPOLATION

–10

–20

–30

–40

–50

–60

–70

–3

–2

–1

Figure 70. Shifted Bandwidths Accessible with the Filter Architecture

With this filter architecture, a signal placed anywhere in the

spectrum is possible. However, the signal bandwidth is limited

by the input sample rate of the DAC and the specific placement

of the carrier in the spectrum. The bandwidth restriction

resulting from the combination of filter response and input

sample rate is often referred to as the synthesis bandwidth, since

this is the largest bandwidth that the DAC can synthesize.

The maximum bandwidth condition exists if the carrier is

placed directly in the center of one of the filter pass bands. In

this case, the total 0.1 dB bandwidth of the interpolation filters

is equal to 0.8 × fDATA. As Table 17 shows, the synthesis band-

width as a fraction of DAC output sample rate drops by a factor

of 2 for every doubling of interpolation rate. The minimum

bandwidth condition exists, for example, if a carrier is placed at

0.25 × fDATA. In this situation, if the nonshifted filter response is

enabled, the high end of the filter response cuts off at 0.4 × fDATA,

thus limiting the high end of the signal bandwidth. If the shifted

filter response is enabled instead, then the low end of the filter

response cuts off at 0.1 × fDATA, thus limiting the low end of the

signal bandwidth. The minimum bandwidth specification that

applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The

minimum bandwidth behavior is repeated over the spectrum

for carriers placed at (±n ± 0.25) × fDATA, where n is any integer.

DRIVING THE REFCLK INPUT

The REFCLK input requires a low jitter differential drive signal.

It is a PMOS input differential pair powered from

the 1.8 V supply, therefore, it is important to maintain the

specified 400 mV input common-mode voltage. Each input

pin can safely swing from 200 mV p-p to 1 V p-p about the

400 mV common-mode voltage. While these input levels are

not directly LVDS-compatible, REFCLK can be driven by an

offset ac-coupled LVDS signal, as shown in Figure 71.

AD9776-EB Datasheet(PDF) 35 Page - Analog Devices

AD9776-EB Datasheet(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL