AD9776-EB datasheet(44/56 Pages) AD

44 / 56 page

AD9776/AD9778/AD9779

Rev. A | Page 44 of 56

Using Data Delay to Meet Timing Requirements

To meet strict timing requirements at input data rates of up to

250 MSPS, the AD977x has a fine timing feature. Fine timing

adjustments are made by programming values into the data

clock delay register (Register 0x04, Bits<7:4>). This register can

be used to add delay between the REFCLK in and the

DATACLK out. Figure 97 shows the default delay present when

DATACLK delay is disabled. The disable function bit is found

in Register 0x02, Bit 4. Figure 98 shows the delay present when

DATACLK delay is enabled and set to 0000. Figure 99 indicates

the delay when DATACLK delay is enabled and set to 1111.

Note that the setup and hold times specified for data to

DATACLK are defined for DATACLK delay disabled.

CH1 1.00V

TEK RUN: 5.00GS/s

SAMPLE

CH2 500mV

M2.00ns

CH1

420mV

Δ: 4.48nS

@: 40.28nS

Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled

CH1 1.00V

TEK RUN: 5.00GS/s

SAMPLE

CH2 500mV

M2.00ns

CH1

420mV

Δ: 4.76nS

@: 35.52nS

Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000

CH1 1.00V

TEK RUN: 5.00GS/s

SAMPLE

CH2 500mV

M2.00ns

CH1

420mV

Δ: 7.84nS

@: 32.44nS

Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111

The difference between the minimum delay shown in Figure 98

and the maximum delay shown in Figure 99 is the range

programmable using the DATACLK delay register. The delay

(in absolute time) when programming DATACLK delay

between 0000 and 1111 is a linear extrapolation between these

two figures. The typical delays per increment over temperature

are shown in Table 20.

Table 20. Data Delay Line Typical Delays Over Temperature

Delays

−40°C

+25°C

+85°C

Unit

Delay Between Disabled and

Enabled

370

416

432

Average Delay per Increment

171

183

197

The frequency of DATACLK out depends on several program-

mable settings: interpolation, zero stuffing, and interleaved/

dual port mode, all of which have an effect on the REFCLK

frequency. The divisor function between REFCLK and

DATACLK is equal to the values shown in Table 21.

Table 21. REFCLK to DATACLK Divisor Ratio

Interpolation

Zero Stuffing

Input Mode

Divisor

Disabled

Dual port

Disabled

Dual port

Disabled

Dual port

Disabled

Dual port

Disabled

Interleaved

Invalid

Disabled

Interleaved

Disabled

Interleaved

Disabled

Interleaved

Enabled

Dual port

Enabled

Dual port

Enabled

Dual port

Enabled

Dual port

Enabled

Interleaved

Enabled

Interleaved

Enabled

Interleaved

Enabled

Interleaved

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