AD9979BCPZ datasheet(16/56 Pages) AD

16 / 56 page

AD9979

Rev. C | Page 16 of 56

HORIZONTAL CLAMPING AND BLANKING

The horizontal clamping and blanking pulses of the AD9979 are

fully programmable to suit a variety of applications. Individual

control is provided for CLPOB, PBLK, and HBLK during the

different regions of each field. This allows the dark-pixel clamping

and blanking patterns to be changed at each stage of the readout

to accommodate the different image transfer timing and high

speed line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK,

as shown in Figure 21. These two signals are independently

programmed using the registers in Table 10. The start polarity

for the CLPOB (PBLK) signal is CLPOB_POL (PBLK_POL),

and the first and second toggle positions of the pulse are

CLPOBx_TOG1 (PBLKx_TOG1) and CLPOBx_TOG2

(PBLKx_TOG2), respectively. Both signals are active low

and need to be programmed accordingly.

Two separate patterns for CLPOB and PBLK can be programmed

for each H-pattern, CLPOB0, CLPOB1, PBLK0, and PBLK1.

The CLPOB_PAT and PBLK_PAT field registers select which

of the two patterns are used in each field.

Figure 32 shows how the sequence change positions divide the

readout field into different regions. By assigning a different

H-pattern to each region, the CLPOB and PBLK signals can

change with each change in the vertical timing.

CLPOB and PBLK Masking Area

Additionally, the AD9979 allows the CLPOB and PBLK signals

to be disabled during certain lines in the field, without changing

any of the existing pattern settings. There are three sets of start

and end registers for both CLPOB and PBLK that allows the

creation of up to three masking areas for each signal.

For example, to use the CLPOB masking, program the

CLPOBMASKSTARTx and CLPOBMASKENDx registers to

specify the starting and ending lines in the field where the

CLPOB patterns are to be ignored. Figure 22 illustrates this

feature.

The masking registers are not specific to a certain H-pattern;

they are always active for any existing field of timing. To disable

the CLPOB and PBLK masking feature, set these registers to the

maximum value of 0x1FFF.

Note that to disable CLPOB and PBLK masking during

power-up, it is recommended to set CLPOBMASKSTARTx

(PBLKMASKSTARTx) to 8191 and CLPOBMASKENDx

(PBLKMASKENDx) to 0. This prevents any accidental masking

caused by different register update events.

CLPOB

PBLK

PROGRAMMABLE SETTINGS:

1START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).

2FIRST TOGGLE POSITION.

3SECOND TOGGLE POSITION.

ACTIVE

Figure 21. Clamp and Preblank Pulse Placement

NO CLPOB SIGNAL

FOR LINE 600

NO CLPOB SIGNAL

FOR LINES 6 TO 8

CLPOBMASKSTART1 = 6

CLPOBMASKEND1 = 8

597

598

CLPOBMASKSTART2 = CLPOBMASKEND2 = 600

CLPOB

Figure 22. CLPOB Masking Example

AD9979BCPZ Datasheet(PDF) 16 Page - Analog Devices

AD9979BCPZ Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL