ICS9LPRS436C

Low Power Clock for Intel Atom

20

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Printed in USA

Revision History

Rev.

Issue Date

Requestor

Description

Page #

0.1

12/14/2009

RDW

Initial Releas e of C rev with updated Frequenc y S elect Table and Updated Idd s pecs for

S uspend State. 48 M LF pinout also added.

-

0.2

12/18/2009

RDW

Corrected IDDPDVDD3.3 param eter to be 0 m A

0.3

1/18/2010

RDW

Updated block diagram

5

0.4

6/1/2010

RDW

Corrected SM Bus as follows:

1. B yte0, bits (4:0) are Read/Write not Read only

2. B yte 6 is as follows: b(7:6) c ontrol P CIe(2:0), b(5:4) control DOT96, b(3:2) control

P CIe3/S ATA , b(1:0) control CP U.

3. A dded '0010 = C rev ' to B yte 7 desc ription for C rev.

4. Updated Abs olute M ax ratings to indicate m ax SM Bus Vhigh is 5.5V.

5. Rem oved IOH and IOL s pecific ations from S ingle E nded output E lectrical

Characteristic s tables. These values are indirectly determined by the Output Term ination

Table.

6. Typic al column added to Electrical Characteristics Tables.

7. General Description updated.

8. References to I2C clarified to refer to SM B us

9. M inor form atting updated to SM Bus B ytes 23, and 25.

5, 8-11,

13,14

A

6/1/2010

RDW

Released to Final