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ICS9LPRS436CKILF Datasheet(PDF) 9 Page - Integrated Device Technology

Part # ICS9LPRS436CKILF
Description  Low Power Clock for Intel Atom짰-Based Systems
PDF  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9LPRS436CKILF Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT®
Low Power Clock for Intel Atom®-Based Systems
1561A — 06/01/10
ICS9LPRS436C
Low Power Clock for Intel Atom
®-Based Systems
9
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Clk Stabilization
TSTAB
From VDD Power-Up or de-assertion of PD to
1st clock
1.8
ms
Tdrive_PEREQ_off
TDRPEROFF
Output stop after PEREQ# deasserted
3
clocks
Tdrive_PEREQ_on
TDRPERON
Output run after PEREQ# asserted
3
clocks
Tdrive_CPU
TDRSRC
CPU output enable after
CPU_STOP# de-assertion
10
ns
Tdrive_PCIEX
TDRPCIEX
PCIEX output enable after
PCI&PCIEX_STOP# de-assertion
15
ns
1
Tfall_SE
TFALL
10
ns
Trise_SE
TRISE
10
ns
Tdrive_PD#
TDRPD
Differential output enable after
PD# de-assertion
300
us
1
Fall/rise time of all 3.3V control inputs from
20-80%
AC Electrical Characteristics - CPU, PCIEX, SATA, DOT96MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
2.5
4
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
2.5
4
V/ns
1,2
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
mV
1
Crossing Point Voltage
VXABS
Single-ended Measurement
300
550
mV
1,3,4
Crossing Point Variation
VXABSVAR
Single-ended Measurement
140
mV
1,3,5
Duty Cycle
DCYC
Differential Measurement
45
55
%
1
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
125
ps
1
SATA Jitter - Cycle to Cycle
SATAJC2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
250
ps
1
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1,6
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1,6
SRC Skew
SRCSKEW
Differential Measurement
250
ps
1
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Output Impedance
RDSP
VO = VDD*(0.5)
12
55
Ω
1
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
2
33.33MHz output no spread
29.99700
30.00300
ns
2
33.33MHz output spread
30.08421
30.23459
ns
2
33.33MHz output no spread
29.49700
30.50300
ns
2
33.33MHz output nominal/spread
29.56617
30.58421
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
V OH @MIN = 1.0 V
-33
mA
1
VOH@MAX = 3.135 V
-33
mA
1
VOL @ MIN = 1.95 V
30
mA
1
VOL @ MAX = 0.4 V
38
mA
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Pin to Pin Skew
tskew
VT = 1.5 V
250
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
1
*T
A = 0 - 70°C; VDD = 3.3 V +/-5%; CL=5pF, Rs=22Ω (unless specified otherwise)
1 Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3 Slew rate emastured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#.
6 CPU group skew is nominally 0ps.
5 Only applies to the differential rising edge (Clock rising, Clock# falling.)
IOH
Output High Current
Tabs
Tperiod
Clock period
Absolute min/max period
Output Low Current
IOL



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