82563EB datasheet(17/52 Pages) INTEL

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82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

3.11

Clock Generator Interface

3.12

Power/Ground Pins

Table 10. Clock Generator Related Signals

Signal Name

Type

Sub-

Type

Description

XTAL1

TTL

25 MHz Clock/Crystal Input

25 MHz +/- 50 ppm input. Can be connected to an oscillator or a

crystal. If using a crystal, XTAL2 must be connected as well. If a

crystal is used, it must be placed within ½-inch of the XTAL1 and

XTAL2 chip pins.

XTAL2

A-o

25 MHz Crystal Output

Output of internal oscillator circuit used to drive crystal into

oscillation. If using an oscillator, XTAL2 is left as a no connect.

PHY_CLK_OUT

TTL8

Clock Output

Output clock available for use by a 631xESB/632xESB or other

component(s).

The speed depends on the how LINK_A is sampled at

LAN_PWR_GOOD assertion:

If LINK_A is 0b, the clock speed is 62.5 MHz.

If LINK_A is 1b, the clock speed is 25 MHz.

The output clock can be disabled depending on how LINK_B is

sampled at LAN_PWR_GOOD assertion:

If LINK_B is 0b: Clock output enabled (pulled-down).

If LINK_B is 1b: Clock output disabled (no connect).

Table 11. Power/Ground Pins (Sheet 1 of 2)

Signal Name

Type

Sub-

Type

Description

VSS

Central

Pad

Ground Exposed-Pad*

The ground is provided through a large central pad on the

bottom side of the package.

VSS

Ground

VDDO

3.3V I/O Ring Power

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