82563EB datasheet(26/52 Pages) INTEL

26 / 52 page

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

4.4.2

Power Sequencing with External Regulators

The following power-on/off sequence should be applied when external power supplies are in use.

Designs must comply with the required power sequence to avoid risk of either latch-up or forward

biased internal diodes.

The general rule of thumb is that the 82563EB/82564EB power sequencing should power up the

three power rails in the following order: 3.3V

1.9V

1.2V. However, if this general guideline

is not followed, there are specific requirements that must be adhered that are listed in the following

two sections.

4.4.2.1

External LVR Power up Sequencing and Tracking

Sequencing of the external supplies during power up may be necessary to ensure that the device is

not electrically overstressed and does not latch-up. These requirements are shown in Figure 3.

• The 82563EB/82564EB core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5V

at any time during the power up. The 82563EB/82564EB core voltage (1.2V) can not exceed

the 1.9V supply by more than 0.5V at any time during the power up. The core voltage is not

required to begin ramping before the 3.3V or the 1.9V supply.

• The 82563EB/82564EB analog voltage (1.9V) cannot exceed the 3.3V supply by more than

0.5V at any time during the power up. The analog voltage is not required to begin ramping

before the 3.3V supply.

Table 20. 1.2V External Power Supply Parameters

Title

Description

Min

Max

Units

Rise Time

Time from 10% to 90% mark

1.5

200

Monotonicity

Voltage dip allowed in ramp

120

Slope

Ramp rate at any given time between

10% and 90%

Min: 0.8*V(min)/Rise time (max)

Max: 0.8*V(max)/Rise time (min)

1500

mV/ms

Operational Range

Voltage range for normal operating

conditions

1.08

1.32

Ripple

Maximum voltage ripple (peak to

peak)a

-100

Overshoot

Maximum overshoot allowed

240

Overshoot Duration

Maximum overshoot allowed

duration.

(At that time delta voltage should be

lower than 5 mV from steady state

voltage)

-1

Decoupling

Capacitance

Capacitance range

µF

Capacitance ESR

Equivalent series resistance of output

capacitance

-100

Ω

a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range. The ripple must be included

within the operational range.

82563EB Datasheet(PDF) 26 Page - Intel Corporation

82563EB Datasheet(HTML) 26 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL