40

35

30

25

20

15

10

5

0

0

100

200

300

400

500

600

700

800

900 1000

Capacitive Load (pF)

+18 V

-18 V

R

ISO

C

L

Device

R

L

G = +1

R

= 0 W

ISO

R

= 25 W

ISO

R

= 50 W

ISO

R =

kW

L

10

40

35

30

25

20

15

10

5

0

0

100

200

300

400

500

600

700

800

900 1000

Capacitive Load (pF)

Device

R =

I

10 kW

R

ISO

C

L

R

+18 V

-18 V

G = 1

-

R

= 0 W

ISO

R

= 25 W

ISO

R

= 50 W

ISO

R = R = 10 kW

L

F

OPA188

SBOS642A – MARCH 2013 – REVISED MARCH 2013

www.ti.com

CAPACITIVE LOAD AND STABILITY

The device dynamic characteristics are optimized for a range of common operating conditions. The combination

of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can lead to gain

peaking or oscillations. As a result, larger capacitive loads must be isolated from the output. The simplest way to

Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus capacitive load for several values of

available for download from www.ti.com, for details of analysis techniques and application circuits.

Figure 41. Small-Signal Overshoot versus

Figure 42. Small-Signal Overshoot versus

Capacitive Load (100-mV Output Step)

Capacitive Load (100-mV Output Step)

ELECTRICAL OVERSTRESS

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.

These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output

pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. See Figure 43 for an illustration of the ESD circuits contained in the OPA188 (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device

internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit

operation.

An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-

current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to

provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the

protection circuitry is then dissipated as heat.

When an ESD voltage develops across two or more amplifier device pins, current flows through one or more

steering diodes. Depending on the path that the current takes, the absorption device may activate. The

absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA188

but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly

activates and clamps the voltage across the supply rails to a safe level.

When the operational amplifier connects into a circuit (such as the one Figure 43 depicts), the ESD protection

components are intended to remain inactive and do not become involved in the application circuit operation.

However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.

Should this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and

conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption

device.

18

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