JS28F128P30TF75A datasheet(55/90 Pages) MICRON

55 / 90 page

Datasheet

Apr 2010

Order Number:208033-02

P30-65nm SBC

Write to Synchronous Read Specifications

W19

tWHCH/L

WE# high to Clock valid

1,2,3,6,10

W20

tWHVH

WE# high to ADV# high

Write Specifications with Clock Active

W21

tVHWL

ADV# high to WE# low

1,2,3,11

W22

tCHWL

Clock high to WE# low

Notes:

Write timing characteristics during erase suspend are the same as write-only operations.

A write operation can be terminated with either CE# or WE#.

Sampled, not 100% tested.

Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high

(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.

Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low

(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).

tWHVH or tWHCH/L must be met when transiting from a write cycle to a synchronous burst read.

VPP and WP# should be at a valid level until erase or program success is determined.

This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20

for synchronous read.

When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.

10.

Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to

reflect this change.

11.

These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.

12.

This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation

to this timing specification.

Figure 25: Write-to-Write Timing

Table 26: AC Write Specifications (Sheet 2 of 2)

Num

Symbol

Parameter

Min

Max

Unit

Notes

Address[A]

CE# [E]

WE# [W]

OE# [G]

Data [D/Q]

RST# [P]

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