JS28F256P30B95A datasheet(27/97 Pages) MICRON

27 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

7.0

Read Operation

The device supports two read modes: asynchronous page mode and synchronous burst

mode. Asynchronous page mode is the default read mode after device power-up or a

reset. The Read Configuration Register must be configured to enable synchronous burst

reads of the flash memory array (see Section 11.2, “Read Configuration Register” on

page 41).

The device can be in any of four read states: Read Array, Read Identifier, Read Status

or Read CFI. Upon power-up, or after a reset, the device defaults to Read Array. To

change the read state, the appropriate read command must be written to the device

(see Section 6.0, “Command Set” on page 24).

7.1

Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page mode is the default read

mode and the device is set to Read Array. However, to perform array reads after any

other device operation (e.g. write operation), the Read Array command must be issued

in order to read from the flash memory array.

Note:

Asynchronous page-mode reads can only be performed when Read Configuration Register bit

RCR[15] is set (see Section 11.2, “Read Configuration Register” on page 41).

To perform an asynchronous page-mode read, an address is driven onto the Address

bus, and CE# and ADV# are asserted. WE# and RST# must already have been

deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven

high to latch the address, or it must be held low throughout the read cycle. CLK is not

used for asynchronous page-mode reads, and is ignored. If only asynchronous reads

are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated

and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial

access time tAVQV delay. (see Section 15.0, “AC Characteristics” on page 55).

In asynchronous page mode, four data words are “sensed” simultaneously from the flash

memory array and loaded into an internal page buffer. The buffer word corresponding

to the initial address on the Address bus is driven onto DQ[15:0] after the initial access

delay. The lowest two address bits determine which word of the 4-word page is output

from the data buffer at any given time.

7.2

Synchronous Burst-Mode Read

To perform a synchronous burst-read, an initial address is driven onto the Address bus,

and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.

ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can

remain asserted throughout the burst access, in which case the address is latched on

the next valid CLK edge while ADV# is asserted.

During synchronous array and non-array read modes, the first word is output from the

data buffer on the next valid CLK edge after the initial access latency delay (see Section

11.2.2, “Latency Count” on page 42). Subsequent data is output on valid CLK edges

following a minimum delay. However, for a synchronous non-array read, the same word

of data will be output on successive clock edges until the burst length requirements are

satisfied. Refer to the following waveforms for more detailed information:

• Figure 24, “Synchronous Single-Word Array or Non-array Read Timing” on page 61

• Figure 25, “Continuous Burst Read, Showing An Output Delay Timing” on page 62

• Figure 26, “Synchronous Burst-Mode Four-Word Read Timing” on page 62

JS28F256P30B95A Datasheet(PDF) 27 Page - Micron Technology

JS28F256P30B95A Datasheet(HTML) 27 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL