JS28F256P30B95A datasheet(43/97 Pages) MICRON

43 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

Figure 13: First-Access Latency Count

Code1

(Reserved

Code6

Code5

Code4

Code3

Code 2

Code0(Reserved)

Code7

Valid

Address

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Address[A]

ADV#[V]

15-0 [D/Q]

CLK[C]

15-0 [D/Q]

Table 20: Latency Count (LC) and Frequency Support

Latency Count Settings

Frequency Support (MHz)

2£ 27

3£ 40

4£ 52

Note:

Synchronous burst read operation is currently not supported for the TSOP package.

JS28F256P30B95A Datasheet(PDF) 43 Page - Micron Technology

JS28F256P30B95A Datasheet(HTML) 43 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL