JS28F256P33BFE datasheet(51/90 Pages) MICRON

51 / 90 page

Datasheet

Aug 2009

Order Number:320003-08

P33-65nm

Note:

WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).

Synchronous Specifications(5)

R301

tAVCH/L

Address setup to CLK

1,6

R302

tVLCH/L

ADV# low setup to CLK

R303

tELCH/L

CE# low setup to CLK

R304

tCHQV / tCLQV CLK to output valid

TSOP

R305

tCHQX

Output hold from CLK

1,6

R306

tCHAX

Address hold from CLK

1,4,6

R307

tCHTV

CLK to WAIT valid

-17

1,6

TSOP

1,6

R311

tCHVL

CLK Valid to ADV# Setup

R312

tCHTX

WAIT Hold from CLK

1,6

Notes:

See

Figure 14, “AC Input/Output Reference Waveform” on page 48 for timing measurements and max

allowable input slew rate.

OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

Sampled, not 100% tested.

Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

Synchronous burst read mode is not supported with TTL level inputs.

Applies only to subsequent synchronous reads.

Table 23: AC Read Specifications - (Sheet 3 of 3)

Num

Symbol

Parameter

Min

Max

Unit

Notes

Figure 17: Asynchronous Single-Word Read (ADV# Low)

R17

R15

Address [A]

ADV#

CE# [E}

OE# [G]

WAIT [T]

Data [D/Q]

RST# [P]

JS28F256P33BFE Datasheet(PDF) 51 Page - Micron Technology

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