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STLUX385ATR Datasheet(PDF) 32 Page - STMicroelectronics |
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STLUX385ATR Datasheet(HTML) 32 Page - STMicroelectronics |
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32 / 99 page ![]() I/O multifunction signal configuration STLUX385A 32/98 DocID024387 Rev 2 Note: Sel_p15…Sel_p10 are common register fields of both registers MISC_IOMXP1 and AFR_IOMXP1. The PWM default polarity level is configured by the register option byte GENCFG. 5.3.1 Port P1 I/O multiplexing signal The next figure shows an outline view of port P1 signal multiplex scheme. Figure 8. Port P1 I/O multiplexing scheme Table 5. Port P1 I/O multiplexing signal Port P1 multifunction configuration signal Output signal Multi-function signal Mux selection Selection bits Value (binary) P1[0] PWM[0] Sel_p10 1 GPIO1[0] 0 P1[1] PWM[1] Sel_p11 1 GPIO1[1] 0 P1[2] PWM[2] Sel_p12 1 GPIO1[2] 0 P1[3] PWM[3] Sel_p13 1 GPIO1[3] 0 P1[4] PWM[4] Sel_p14 1 GPIO1[4] 0 P1[5] PWM[5] Sel_p15 1 GPIO1[5] 0 INPUT OUTPUT PWM out P1_IDR[5:0] P1_ODR[5:0] -MSC_IOMXP1 -AFR_IOMXP1 PWM[5..0] P1[5:0] GIPC080520131642FSR |
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