AD822 datasheet(37/88 Pages) AD

37 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 37 of 88

CFG841

ADuC841 Config SFR

SFR Address

AFH

Power-On Default

10H1

Bit Addressable

Table 14. CFG841 SFR Bit Designations

Bit No.

Name

Description

EXSP

Extended SP Enable.

When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H.

When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.

PWPO

PWM Pin Out Selection.

Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins.

Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins.

DBUF

DAC Output Buffer.

Set to 1 by the user to bypass the DAC output buffer.

Set to 0 by the user to enable the DAC output buffer.

EPM2

Flash/EE Controller and PWM Clock Frequency Configuration Bits.

Frequency should be configured such that FOSC/Divide Factor = 32 kHz + 50%.

EPM1

EPM0

EPM2

EPM1

EPM0

Divide Factor

128

256

512

1024

MSPI

Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5,

respectively.

Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins.

XRAMEN

XRAM Enable Bit.

When set to 1 by the user, the internal XRAM is mapped into the lower two kBytes of the external address

space.

When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is mapped into

the lower two kBytes of external data memory.

1 Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their correct values depending on the crystal frequency at power-up. The user should not modify

these bits so all instructions to the CFG841 register should use the ORL, XRL, or ANL instructions. Value of 10H is for 11.0592 MHz crystal.

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