AD822 datasheet(45/88 Pages) AD

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ADuC841/ADuC842/ADuC843

Rev. 0 | Page 45 of 88

SERIAL PERIPHERAL INTERFACE (SPI)

The ADuC841/ADuC842/ADuC843 integrate a complete hard-

ware serial peripheral interface on-chip. SPI is an industry-

standard synchronous serial interface that allows 8 bits of data

to be synchronously transmitted and received simultaneously,

i.e., full duplex. Note that the SPI pins are shared with the I2C

pins. Therefore, the user can enable only one interface or the

other on these pins at any given time (see SPE in Table 18). SPI

can be operated at the same time as the I2C interface if the

MSPI bit in CFG841/CFG8842 is set. This moves the SPI

outputs (MISO, MOSI, and SCLOCK) to P3.3, P3.4, and P3.5,

respectively). The SPI port can be configured for master or slave

operation and typically consists of four pins, described in the

following sections.

MISO (Master In, Slave Out Data I/O Pin)

The MISO pin is configured as an input line in master mode

and as an output line in slave mode. The MISO line on the

master (data in) should be connected to the MISO line in the

slave device (data out). The data is transferred as byte-wide

(8-bit) serial data, MSB first.

MOSI (Master Out, Slave In Pin)

The MOSI pin is configured as an output line in master mode

and as an input line in slave mode. The MOSI line on the master

(data out) should be connected to the MOSI line in the slave

device (data in). The data is transferred as byte-wide (8-bit)

serial data, MSB first.

SCLOCK (Serial Clock I/O Pin)

The master serial clock (SCLOCK) is used to synchronize the

data being transmitted and received through the MOSI and

MISO data lines. A single data bit is transmitted and received in

each SCLOCK period. Therefore, a byte is transmitted/received

after eight SCLOCK periods. The SCLOCK pin is configured as

an output in master mode and as an input in slave mode. In

master mode, the bit rate, polarity, and phase of the clock are

controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the

SPICON SFR (see Table 18). In slave mode, the SPICON register

must be configured with the phase and polarity (CPHA and

CPOL) of the expected input clock. In both master and slave

modes, the data is transmitted on one edge of the SCLOCK

signal and sampled on the other. It is important, therefore, that

CPHA and CPOL are configured the same for the master and

slave devices.

SS (Slave Select Input Pin)

The SS pin is shared with the ADC5 input. To configure this pin

as a digital input, the bit must be cleared, e.g., CLR P1.5. This

line is active low. Data is received or transmitted in slave mode

only when the SS pin is low, allowing the parts to be used in

single-master, multislave SPI configurations. If CPHA = 1, the

SS input may be permanently pulled low. If CPHA = 0, the SS

input must be driven low before the first bit in a byte-wide

transmission or reception and return high again after the last bit

in that byte-wide transmission or reception. In SPI slave mode,

the logic level on the external SS pin can be read via the SPR0

bit in the SPICON SFR. The SFR registers, described in the

following tables, are used to control the SPI interface.

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