DSPIC33FJ32GP302THSLASHSP datasheet(207/403 Pages) MICROCHIP

207 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 207

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

17.0

INTER-INTEGRATED

CIRCUIT™ (I2C™)

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

The I2C module has a 2-pin interface:

• The SCLx pin is clock.

• The SDAx pin is data.

The I2C module offers the following key features:

•I2C interface supporting both Master and Slave

modes of operation.

•I2C Slave mode supports 7 and 10-bit address.

•I2C Master mode supports 7 and 10-bit address.

•I2C Port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I2C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

•I2C supports multi-master operation, detects bus

collision and arbitrates accordingly.

17.1

Operating Modes

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

The I2C module can operate either as a slave or a

master on an I2C bus.

The following types of I2C operation are supported:

•I2C slave operation with 7-bit address

•I2C slave operation with 10-bit address

•I2C master operation with 7- or 10-bit address

For details about the communication sequence in each

of these modes, refer to the “dsPIC33F/PIC24H Family

Reference Manual”. Please see the Microchip website

(www.microchip.com) for the latest dsPIC33F Family

Reference Manual chapters.

17.2

I2C Registers

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write:

• I2CxRSR is the shift register used for shifting data

internal to the module and the user application

has no access to it.

• I2CxRCV is the receive buffer and the register to

which data bytes are written, or from which data

bytes are read.

• I2CxTRN is the transmit register to which bytes

are written during a transmit operation.

• The I2CxADD register holds the slave address.

• A status bit, ADD10, indicates 10-bit Address

mode.

• The I2CxBRG acts as the Baud Rate Generator

(BRG) reload value.

In receive operations, I2CxRSR and I2CxRCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV,

and an interrupt pulse is generated.

Note 1: This data sheet summarizes the features

the

dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04,

and

dsPIC33FJ128GPX02/X04

families

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to “Section 19. Inter-Integrated

Circuit™ (I2C™)” (DS70195) of the

“dsPIC33F/PIC24H

Family

Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers

and

associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 207 Page - Microchip Technology

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