DSPIC33FJ32GP302THSLASHSP datasheet(210/403 Pages) MICROCHIP

210 / 403 page

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292D-page 210

Preliminary

 2009 Microchip Technology Inc.

bit 5

ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

= Send NACK during Acknowledge

= Send ACK during Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit

(when operating as I2C master, applicable during master receive)

= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Hardware clear at end of master Acknowledge sequence

= Acknowledge sequence not in progress

bit 3

RCEN: Receive Enable bit (when operating as I2C master)

= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte

= Receive sequence not in progress

bit 2

PEN: Stop Condition Enable bit (when operating as I2C master)

= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence

= Stop condition not in progress

bit 1

RSEN: Repeated Start Condition Enable bit (when operating as I2C master)

= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of

master Repeated Start sequence

= Repeated Start condition not in progress

bit 0

SEN: Start Condition Enable bit (when operating as I2C master)

= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence

= Start condition not in progress

I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 210 Page - Microchip Technology