DSPIC33FJ32GP302THSLASHSP datasheet(294/403 Pages) MICROCHIP

294 / 403 page

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292D-page 294

Preliminary

 2009 Microchip Technology Inc.

PMMODE: PARALLEL PORT MODE REGISTER

R-0

R/W-0

BUSY

IRQM<1:0>

INCM<1:0>

MODE16

MODE<1:0>

bit 15

bit 8

R/W-0

WAITB<1:0>(1)

WAITM<3:0>

WAITE<1:0>(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

BUSY: Busy bit (Master mode only)

= Port is busy (not useful when the processor stall is active)

= Port is not busy

bit 14-13

IRQM<1:0>: Interrupt Request Mode bits

= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)

= No interrupt generated, processor stall activated

= Interrupt generated at the end of the read/write cycle

= No interrupt generated

bit 12-11

INCM<1:0>: Increment Mode bits

= PSP read and write buffers auto-increment (Legacy PSP mode only)

= Decrement ADDR<10:0> by 1 every read/write cycle

= Increment ADDR<10:0> by 1 every read/write cycle

= No increment or decrement of address

bit 10

MODE16: 8-Bit/16-Bit Mode bit

= 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers

= 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer

bit 9-8

MODE<1:0>: Parallel Port Mode Select bits

= Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

= Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

= Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)

= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)

bit 7-6

WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1)

= Data wait of 4 TCY; multiplexed address phase of 4 TCY

= Data wait of 3 TCY; multiplexed address phase of 3 TCY

= Data wait of 2 TCY; multiplexed address phase of 2 TCY

= Data wait of 1 TCY; multiplexed address phase of 1 TCY

bit 5-2

WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits

1111

= Wait of additional 15 TCY

•

0001

= Wait of additional 1 TCY

0000

= No additional wait cycles (operation forced into one TCY)

bit 1-0

WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1)

= Wait of 4 TCY

= Wait of 3 TCY

= Wait of 2 TCY

= Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 294 Page - Microchip Technology

DSPIC33FJ32GP302TH/SP Datasheet(HTML) 294 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL