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DSPIC33FJ32GP302TH/SP Datasheet(PDF) 291 Page - Microchip Technology

Part # DSPIC33FJ32GP302TH/SP
Description  High-Performance, 16-bit Digital Signal Controllers
PDF  403 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33FJ32GP302TH/SP Datasheet(HTML) 291 Page - Microchip Technology

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 2009 Microchip Technology Inc.
Preliminary
DS70292D-page 291
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
26.0
PARALLEL MASTER PORT
(PMP)
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
Key features of the PMP module include:
• Fully multiplexed address/data mode
• Demultiplexed or partially multiplexed address/
data mode
- up to 11 address lines with single chip select
- up to 12 address lines without chip select
• One Chip Select Line
• Programmable Strobe Options
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
FIGURE 26-1:
PMP MODULE OVERVIEW
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04
families
of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 35. Parallel Master
Port
(PMP)”
(DS70299)
of
the
“dsPIC33F/PIC24H
Family
Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers
and
associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
PMA<0>
PMBE
PMRD
PMWR
PMD<7:0>
PMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<10:2>(1)
PMALL
PMALH
PMA<7:0>
PMA<10:8>
EEPROM
Address Bus
Data Bus
Control Lines
dsPIC33F
LCD
FIFO
Microcontroller
8-Bit Data
Up to 11-Bit Address
Parallel Master Port
Buffer
Note 1: 28-pin devices do not have PMA<10:2>.
PMA<14>



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