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DSPIC33FJ32GP302TH/SP Datasheet(PDF) 146 Page - Microchip Technology |
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DSPIC33FJ32GP302TH/SP Datasheet(HTML) 146 Page - Microchip Technology |
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146 / 403 page ![]() dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 146 Preliminary 2009 Microchip Technology Inc. bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. |
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