DSPIC33FJ32GP302THSLASHSP datasheet(145/403 Pages) MICROCHIP

145 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 145

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

OSCCON: OSCILLATOR CONTROL REGISTER(1)

U-0

R-0

U-0

R/W-y

—COSC<2:0>

—NOSC<2:0>(2)

bit 15

bit 8

R/W-0

R-0

U-0

R/C-0

U-0

R/W-0

CLKLOCK

IOLOCK

LOCK

—CF

—

LPOSCEN

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

C = Clear only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

000

= Fast RC oscillator (FRC)

001

= Fast RC oscillator (FRC) with PLL

010

= Primary oscillator (XT, HS, EC)

011

= Primary oscillator (XT, HS, EC) with PLL

100

= Secondary oscillator (SOSC)

101

= Low-Power RC oscillator (LPRC)

110

= Fast RC oscillator (FRC) with Divide-by-16

111

= Fast RC oscillator (FRC) with Divide-by-n

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits(2)

000

= Fast RC oscillator (FRC)

001

= Fast RC oscillator (FRC) with PLL

010

= Primary oscillator (XT, HS, EC)

011

= Primary oscillator (XT, HS, EC) with PLL

100

= Secondary oscillator (SOSC)

101

= Low-Power RC oscillator (LPRC)

110

= Fast RC oscillator (FRC) with Divide-by-16

111

= Fast RC oscillator (FRC) with Divide-by-n

bit 7

CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)

= Clock switching is disabled, system clock source is locked

= Clock switching is enabled, system clock source can be modified by clock switching

bit 6

IOLOCK: Peripheral Pin Select Lock bit

= Peripherial pin select is locked, write to peripheral pin select registers not allowed

= Peripherial pin select is not locked, write to peripheral pin select registers allowed

bit 5

LOCK: PLL Lock Status bit (read-only)

= Indicates that PLL is in lock, or PLL start-up timer is satisfied

= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

Unimplemented: Read as ‘0’

bit 3

CF: Clock Fail Detect bit (read/clear by application)

= FSCM has detected clock failure

= FSCM has not detected clock failure

Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216)

in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC mode

as a transition clock source between the two PLL modes.

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 145 Page - Microchip Technology

DSPIC33FJ32GP302TH/SP Datasheet(HTML) 145 Page - Microchip Technology

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