DSPIC33FJ32GP302THSLASHSP datasheet(190/403 Pages) MICROCHIP

190 / 403 page

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292D-page 190

Preliminary

 2009 Microchip Technology Inc.

The Timer2/3 and Timer4/5 modules can operate in

one of the following modes:

•Timer mode

• Gated Timer mode

• Synchronous Counter mode

In Timer and Gated Timer modes, the input clock is

derived from the internal instruction cycle clock (FCY).

In Synchronous Counter mode, the input clock is

derived from the external clock input at TxCK pin.

The timer modes are determined by the following bits:

• TCS (TxCON<1>): Timer Clock Source Control bit

• TGATE (TxCON<6>): Timer Gate Control bit

Timer control bit settings for different operating modes

are given in the Table 13-1.

TABLE 13-1:

TIMER MODE SETTINGS

13.1

16-Bit Operation

To configure any of the timers for individual 16-bit

operation:

Clear the T32 bit corresponding to that timer.

Select the timer prescaler ratio using the

TCKPS<1:0> bits.

Set the Clock and Gating modes using the TCS

and TGATE bits.

Load the timer period value into the PRx

If interrupts are required, set the interrupt enable

bit, TxIE. Use the priority bits, TxIP<2:0>, to set

the interrupt priority.

Set the TON bit.

13.2

32-Bit Operation

A 32-bit timer module can be formed by combining a

Type B and a Type C 16-bit timer module. For 32-bit

timer operation, the T32 control bit in the Type B Timer

Control (TxCON<3>) register must be set. The Type C

timer holds the most significant word (msw) and the

Type B timer holds the least significant word (lsw) for

32-bit operation.

When configured for 32-bit operation, only the Type B

Timer Control (TxCON) register bits are required for

setup and control. Type C timer control register bits are

ignored (except TSIDL bit).

For interrupt control, the combined 32-bit timer uses

the interrupt enable, interrupt flag and interrupt priority

control bits of the Type C timer. The interrupt control

and status bits for the Type B timer are ignored during

32-bit timer operation.

The Type B and Type C timers that can be combined to

form a 32-bit timer are listed in Table 13-2.

TABLE 13-2:

32-BIT TIMER

A block diagram representation of the 32-bit timer mod-

ule is shown in Figure 13-3. The 32-bit timer module

can operate in one of the following modes:

• Timer mode

• Gated Timer mode

• Synchronous Counter mode

To configure the features of Timer2/3 or Timer4/5 for

32-bit operation:

Set the T32 control bit.

Select the prescaler ratio for Timer2 or Timer4

using the TCKPS<1:0> bits.

Set the Clock and Gating modes using the

corresponding TCS and TGATE bits.

Load the timer period value. PR3 or PR5 con-

tains the most significant word of the value,

while PR2 or PR4 contains the least significant

word.

If interrupts are required, set the interrupt enable

bits, T3IE or T5IE. Use the priority bits,

T3IP<2:0> or T5IP<2:0> to set the interrupt pri-

ority. While Timer2 or Timer4 controls the timer,

the interrupt appears as a Timer3 or Timer5

interrupt.

Set the corresponding TON bit.

The timer value at any point is stored in the register

pair, TMR3:TMR2 or TMR5:TMR4, which always

contains the most significant word of the count, while

TMR2 or TMR4 contains the least significant word.

Mode

TCS

TGATE

Timer

Gated timer

Synchronous coun-

ter

Note:

Only Timer2 and Timer3 can trigger a

DMA data transfer.

TYPE B Timer (lsw)

TYPE C Timer (msw)

Timer2

Timer3

Timer4

Timer5

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 190 Page - Microchip Technology

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