DSPIC33FJ32GP302THSLASHSP datasheet(193/403 Pages) MICROCHIP

193 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 193

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

TxCON: TIMER CONTROL REGISTER (x = 3 OR 5)

R/W-0

U-0

R/W-0

U-0

TON(2)

—TSIDL(1)

—

bit 15

bit 8

U-0

R/W-0

U-0

R/W-0

U-0

—

TGATE(2)

TCKPS<1:0>(2)

—

—TCS(2)

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

TON: Timery On bit(2)

= Starts 16-bit Timer

= Stops 16-bit Timer

bit 14

Unimplemented: Read as ‘0’

bit 13

TSIDL: Stop in Idle Mode bit(1)

= Discontinue timer operation when device enters Idle mode

= Continue timer operation in Idle mode

bit 12-7

Unimplemented: Read as ‘0’

bit 6

TGATE: Timer

x Gated Time Accumulation Enable bit(2)

When TCS = 1:

This bit is ignored.

When TCS = 0:

= Gated time accumulation enabled

= Gated time accumulation disabled

bit 5-4

TCKPS<1:0>: Timer

x Input Clock Prescale Select bits(2)

= 1:256 prescale value

= 1:64 prescale value

= 1:8 prescale value

= 1:1 prescale value

bit 3-2

Unimplemented: Read as ‘0’

bit 1

TCS: Timer

x Clock Source Select bit(2)

= External clock from TxCK pin

= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit

must be cleared to operate the 32-bit timer in Idle mode.

2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits

have no effect.

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 193 Page - Microchip Technology

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