DSPIC33FJ32GP302THSLASHSP datasheet(195/403 Pages) MICROCHIP

195 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 195

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

14.0

INPUT CAPTURE

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/

X04, and dsPIC33FJ128GPX02/X04 devices support

up to four input capture channels.

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

Simple Capture Event modes:

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

Capture timer value on every edge (rising and

falling)

Prescaler Capture Event modes:

- Capture timer value on every 4th rising edge

of input at ICx pin

- Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select one of two 16-

bit timers (Timer2 or Timer3) for the time base. The

selected timer can use either an internal or external

clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

- Interrupt optionally generated after 1, 2, 3 or

4 buffer locations are filled

• Use of input capture to provide additional sources

of external interrupts

FIGURE 14-1:

INPUT CAPTURE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

the

dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04,

and

dsPIC33FJ128GPX02/X04

families

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to “Section 12. Input Capture”

(DS70198) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is avail-

able

from

the

Microchip

website

(www.microchip.com).

2: Some registers

and

associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

Note:

Only IC1 and IC2 can trigger a DMA data

transfer.

DMA

data

transfers

are

required, the FIFO buffer size must be set

to ‘1’ (ICI<1:0> = 00)

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

FIFO CONTROL

ICxBUF

TMR2

TMR3

CaptureEvent

FIFO

ICI<1:0>

ICM<2:0>

101

100

011

010

001

111

To CPU

Set Flag ICxIF

(In IFSx Register)

Rising Edge Mode

Prescaler Mode

(4th Rising Edge)

Falling Edge Mode

Edge Detection

Prescaler Mode

(16th Rising Edge)

Sleep/Idle

Wake-up Mode

ICTMR

ICx pin

Mode

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 195 Page - Microchip Technology

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