MPC8358ECVRADDDA datasheet(48/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

I2C AC Electrical Specifications

11.2

I2C AC Electrical Specifications

This table provides the AC timing parameters for the I2C interface of the device.

Table 45. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 44).

Parameter

Symbol1

Min

Max

Unit

Note

SCL clock frequency

fI2C

400

kHz

Low period of the SCL clock

tI2CL

1.3

—

μs—

High period of the SCL clock

tI2CH

0.6

—

μs—

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs—

Hold time (repeated) START condition (after this period, the

first clock pulse is generated)

tI2SXKL

0.6

—

μs—

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0.93

μs—

Rise time of both SDA and SCL signals

tI2CR

20 + 0.1 Cb

300

—

Fall time of both SDA and SCL signals

tI2CF

20 + 0.1 Cb

300

—

Set-up time for STOP condition

tI2PVKH

0.6

—

μs—

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs—

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OVDD

—V

—

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH

0.2

× OVDD

—V

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional

block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For

example, tI2DVKH symbolizes I

2C timing (I2) with respect to the time data input signals (D) reach the valid state (V)

relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing

(I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock

reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

2C timing (I2) for the time that the

data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going

to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

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