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AD9974BBCZ Datasheet(PDF) 41 Page - Analog Devices |
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AD9974BBCZ Datasheet(HTML) 41 Page - Analog Devices |
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41 / 52 page  AD9974 Rev. A | Page 41 of 52 UPDATING OF REGISTER VALUES The internal registers of the AD9974 are updated at different times, depending on the particular register. Table 21 summarizes the three types of register updates. The tables in the Complete Register Listing section also contain a column with update type to identify when each register is updated. • SCK Updated—Some of the registers are updated immediately as the 28th data bit (D27) is written. These registers are used for functions that do not require gating with the next VD boundary, such as power-up and reset functions. • VD Updated—Many of the registers are updated at the next VD falling edge. By updating these values at the next VD edge, the current field is not corrupted, and the new register values are applied to the next field. The VD update can be further delayed past the VD falling edge by using UPDATE Register Address 0x17. This delays the VD-updated register updates to any HD line in the field. Note that the field registers are not affected by the UPDATE register. • SCP Updated—All of the H-pattern group registers are updated at the next SCP when they are used. Table 21. Register Update Types Update Type Description SCK Updated Register is immediately updated when the 28th data bit (D27) is clocked in. VD Updated Register is updated at the VD falling edge. VD-updated registers can be delayed further by using the UPDATE register at Address 0x17. Field registers are not affected by the UPDATE register. SCP Updated Register is updated at the next SCP when the register is used. |
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