AMC7812SPAPR datasheet(77/92 Pages) TI

77 / 92 page

AMC7812

www.ti.com

SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

TEMPERATURE THRESHOLD REGISTERS

LT-High-Threshold Register (Read/Write, Address = 62h, Default = 07FFh, +255.875°C)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THRH

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

LT-Low-Threshold Register (Read/Write, Address = 63h, Default = 0800h, –256°C)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THRL

Bits [15:12] = Reserved. Writing to these bits causes no change. Reading these bits returns '0'.

D1-High-Threshold Register (Read/Write, Address = 64h, Default = 07FFh, +255.875°C)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THRH

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

D1-Low-Threshold Register (Read/Write, Address = 65h, Default = 0800h, –256°C)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THRL

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

D2-High-Threshold Register (Read/Write, Address = 66h, Default = 07FFh, +255.875°C)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THRH

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

D2-Low-Threshold Register (Read/Write, Address = 67h, Default = 0800h, –256°C)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THRL

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

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