L-Channel

R-Channel

LRCK

SLCK

DATA

N−1

N−2

N−3

0

N−1

N−2

N−3

0

1

2

MSB

LSB

LSB

MSB

1

2

N–1

N–2

LRCK

MSB

LSB

MSB

LSB

LSB

LSB

L-Channel

R-Channel

SCLK

DATA

2

1

0

2

1

0

2

1

0

2

1

0

2

1

0

DATA

DATA

DATA

17 16 15

2

1

0

2

1

0

19 18 17

2

1

0

MSB

LSB

MSB

LSB

LSB

MSB

LSB

15 14 13

2

1

0

2

1

0

17 16 15

2

1

0

19 18 17

2

1

0

MSB

15 14 13

MSB

15 14 13

MSB

15 14 13

LSB

DATA

2

1

0

2

1

0

MSB

LSB

23 22 21

2

1

0

MSB

23 22 21

LSB

2

1

0

2

1

0

DATA

LSB

2

1

0

MSB

23 22 21

MSB

23 22 21

TAS5704

www.ti.com

SLOS563A – MARCH 2008 – REVISED AUGUST 2010

Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it

is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,

toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused

trailing data bit positions.

Figure 27. Left-Justified Format

Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before

LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks

unused leading data bit positions.

Figure 28. Right-Justified Format

Copyright © 2008–2010, Texas Instruments Incorporated

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