TAS5704PAPR datasheet(6/39 Pages) TI1

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TAS5704

SLOS563A – MARCH 2008 – REVISED AUGUST 2010

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PIN FUNCTIONS (continued)

5-V

TERMINATION

TYPE

DESCRIPTION

TOLERANT

(2)

NAME

NO.

(1)

BST_B

High-side bootstrap supply for half-bridge B

BST_C

High-side bootstrap supply for half-bridge C

BST_D

High-side bootstrap supply for half-bridge D

BYPASS

Nominally equal to VCC/8. Internal reference voltage for analog cells

CONFIG_1

Pulldown

Input/output configuration.

CONFIG_2

Pulldown

Input/output configuration.

DVDD

15,

3.3-V digital power supply

DVSS

Digital ground

DVSSO

Oscillator ground

FORMAT0

Pulldown

Digital data format select.

FORMAT1

Pulldown

Digital data format select.

FORMAT2

Digital data format select.

GAIN_0

LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain

selections.

GAIN_1

MSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain

selections.

LRCLK

5-V

Input serial audio data left/right clock (sampling rate clock)

MCLK

5-V

Master clock input. The input frequency of this clock can range from

4.9 MHz to 49.2 MHz.

MUTE

5-V

Pullup

Performs a soft mute of outputs, active-low. A logic low on this

terminal sets the outputs equal to 50% duty cycle. A logic high on this

terminal allows normal operation. The mute control provides a

noiseless volume ramp to silence. Releasing mute provides a

noiseless ramp to previous volume.

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω resistor to DVSSO.

OUT_A

4, 5

Output, half-bridge A

OUT_B

1, 64

Output, half-bridge B

OUT_C

49,

Output, half-bridge C

OUT_D

45,

Output, half-bridge D

PDN

5-V

Pullup

Power down, active-low. PDN stops all clocks and outputs stop

switching. When PDN is released, the device powers up all logic,

starts all clocks, and performs a soft start that returns to the previous

configuration. Changes to CONFIG_x, FORMATx, and GAIN_x pins

are ignored on PDN cycling.

PGND_A

6, 7

Power ground for half-bridge A

PGND_B

2, 3

Power ground for half-bridge B

PGND_C

47,

Power ground for half-bridge C

PGND_D

43,

Power ground for half-bridge D

PLL_FLTM

PLL negative loop filter terminal

PLL_FLTP

PLL positive loop filter terminal

PVCC_A

8, 9

Power supply input for half-bridge output A

PVCC_B

62,

Power supply input for half-bridge output B

PVCC_C

51,

Power supply input for half-bridge output C

PVCC_D

41,

Power supply input for half-bridge output D

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