DM3725CBC datasheet(139/280 Pages) TI

139 / 280 page

SWPS038-011

sys_clkout1

CO0

CO1

DM3730, DM3725

www.ti.com

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

Table 4-11. sys_clkout1 Output Clock Switching Characteristics(6) (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

tF(CLKOUT1)

Fall time, sys_clkout1

0.4(2) (4)

5(3)

(1) The mode is configured by bits SC0 and SC1 of the IO cell. For more details, see the AM/DM37x Multimedia Device Technical

Reference Manual (SPRUGN4).

(2) At minimum load

(3) At maximum load (Maximum frequency 20 MHz)

(4) Caution: this creates EMI parasitics up to 1.2 ns

(5) X parameter corresponds to the input jitter contribution added at sys_xtalin input pin. For more information regarding the sys_xtalin input

jitter requirement, see Section 4.1.1.

(6) In this table, the transition times are calculated for 10%-90% of VDDS. For more information on the corresponding VDDS power supply

name, please see the Ball Characteristics table corresponding to your package. The POWER column defines the VDDS power supply

for each ball.

Figure 4-6. sys_clkout1 Output Clock

4.2.2

sys_clkout2 Output Clock

Table 4-12 summarizes the sys_clkout2 ouput clock electrical characteristics.

Table 4-12. sys_clkout2 Output Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency, sys_clkout2

sys_xtalin clock or core_dpll clock(1) or 54

MHz

MHz, 96 MHz(2)

Load capacitance

Transmission line impedance

Ω

Transmission line length

(1) Possible divider: 4, 8, or 16.

(2) Possible divider: 1, 2, 4, 8, or 16.

Table 4-13 details the sys_clkout2 ouput clock switching characteristics.

Table 4-13. sys_clkout2 Output Clock Switching Characteristics(8)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

CO0

1 / tc(CLKOUT2) Frequency, sys_clkout2

sys_xtalin clock or core_dpll clock(3) or 54

MHz

MHz, 96 MHz(4)

tc(xtalin)

Cycle time, sys_xtalin

1 / sys_xtalin

(MHz)

tc(coredpll)

Cycle time, core_dpll (DPLL3) (7)

1 / core_dpll

(MHz)

tc(54mhz)

Cycle time, 54MHz clock (DPLL4) (7)

18.52

tc(96mhz)

Cycle time, 96MHz clock (DPLL4) (7)

10.42

CO1

tw(CLKOUT2)

Pulse duration, sys_clkout2 low or high

0.49*tc(clkout

0.51*tc(clkout

Clock Specifications

139

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