DM3725CBC datasheet(140/280 Pages) TI

140 / 280 page

SWPS038-012

sys_clkout2

CO0

CO1

DM3730, DM3725

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

www.ti.com

Table 4-13. sys_clkout2 Output Clock Switching Characteristics(8) (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

(5)

Peak-to-peak jitter

Source clock:

X%(6) *

sys_xtalin

tc(xtalin) + 200

Source clock:

4% *

core_dpll

tc(coredpll) +

200

Source clock: 54MHz

4% * tc(54mhz)

+ 200

Source clock: 96MHz

4% * tc(96mhz)

+ 200

tR(CLKOUT2)

Rise time, sys_clkout2

1.5(1)

5(2)

tF(CLKOUT2)

Fall time, sys_clkout2

1.5(1)

5(2)

(1) At minimum load

(2) At maximum load (maximum frequency 104 MHz)

(3) Possible divider: 4, 8, 16

(4) Possible divider: 1, 2, 4, 8, or 16

(5) Peak-to-peak jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

–

The minimum value is the difference between the shortest measured clock period and the expected clock period

Maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock

period.

(6) Depending on the internal system clock divider configuration (PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bit field), the sys_xtalin

input clock can be divided by 2 to provide the standard system clock (SYS_CLK) frequencies. For more information, see the Power,

Reset, and Clock Management / PRCM Functional Description / PRCM Clock Manager Functional Description / External Clock I/Os /

External Clock Inputs / High-Frequency System Clock section of AM/DM37x Multimedia Device Technical Reference Manual (literature

number SPRUGN4).

In X%, X represents then the internal system clock divider with following possible values: X = 1 or 2.

(7) This cycle time specified here is the clock period of the clock going out of sys_clkout2.

(8) In this table, the transition times are calculated for 10%-90% of VDDS. For more information on the corresponding VDDS power supply

name, please see the Ball Characteristics table corresponding to your package. The POWER column defines the VDDS power supply

for each ball.

Figure 4-7. sys_clkout2 Output Clock

4.3

DPLL and DLL Specifications

NOTE

For more information, see Power, Reset, and Clock Management / PRCM Functional

Description / PRCM Clock Manager Functional Description / Internal Clock Generation /

DPLLs section of the AM/DM37x Multimedia Device Technical Reference Manual

(SPRUGN4).

The applicative subsystem integrates six DPLLs and a DLL. The PRM and CM drive those listed below.

The main DPLLs are:

•

DPLL1 (MPU)

•

DPLL2 (IVA)

•

DPLL3 (Core)

•

DPLL4 (Peripherals)

•

DPLL5 (Second peripherals DPLL)

140

Clock Specifications

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